Change in ...coreboot[master]: mb/google/hatch: Enable SATA for Hatch

[V Sowmya (Code Review)]

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30435

Change subject: mb/google/hatch: Enable SATA for Hatch
......................................................................

mb/google/hatch: Enable SATA for Hatch

This patch enables the SATA for hatch,
* Enable the SATA port 1.
* Configure the GPIO for SATA.

Change-Id: Iaf800d1531688c3d3b82600038ea1d7160ae4b0b
Signed-off-by: V Sowmya 
---
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
M src/mainboard/google/hatch/variants/baseboard/gpio.c
2 files changed, 16 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/30435/1

diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index ff48b54..5330f4d 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -39,6 +39,12 @@
    # FSP configuration
    register "InternalGfx" = "1"
    register "SkipExtGfxScan" = "1"
+        register "SataSalpSupport" = "1"
+        register "SataMode" = "Sata_AHCI"
+        register "SataPortsEnable[1]" = "1"
+        register "SataPortsDevSlp[1]" = "1"
+        register "satapwroptimize" = "1"
+

# Enable Root port 9(x4) for NVMe.
    # Enable CLKREQ#
@@ -75,7 +81,7 @@
    	device pci 16.3 off end # Management Engine KT Redirection
    	device pci 16.4 off end # Management Engine Interface 3
    	device pci 16.5 off end # Management Engine Interface 4
-		device pci 17.0 off end # SATA
+		device pci 17.0 on  end # SATA
    	device pci 19.0 off end # I2C #4
    	device pci 19.1 off end # I2C #5
    	device pci 19.2 off end # UART #2
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index ba7f734..346af0d 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -49,6 +49,15 @@
    PAD_CFG_GPI(GPP_F11, NONE, PLTRST),
    /* PCH_MEM_STRAP3 */
    PAD_CFG_GPI(GPP_F22, NONE, PLTRST),
+	/* SATAGP1 */
+	PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2),
+	/*
+	 * M2_SSD_PE_WAKE_ODL This pin is not connected because of the resistor
+	 * unstuff.
+	 */
+	PAD_CFG_GPO(GPP_E4, 1, DEEP),
+	/* SATA_DEVSLP1 */
+	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
    /* USB_C0_DP_HPD */
    PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
    /* DDI2_HPD_ODL */