Patch set updated for coreboot: 07cabfb superio/winbond/w83627hf: Avoid .c includes in mainboards
Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5601
-gerrit
commit 07cabfb5ca9e4029a591204538e349227726d0f4 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Tue Apr 29 13:09:50 2014 +1000
superio/winbond/w83627hf: Avoid .c includes in mainboards
Move towards the removal of the superio model specific xxx_serial_enable implementation. Make remaining superio romstage parts link-time symbols and fix corresponding mainboards to match.
The following mainboards remain unconverted as they are ROMCC: - mainboard/supermicro/x6dai_g - mainboard/supermicro/x6dhe_g - mainboard/supermicro/x6dhr_ig - mainboard/supermicro/x6dhr_ig2 and so block the final removal of w83627hf_serial_enable().
Special cases: - mainboard/supermicro/h8qme_fam10: Provide local pnp_ sio func - mainboard/kontron/986lcd-m: Provide local pnp_ sio func Provide local superio pnp_ programming entry/exit functions as to avoid making superio implementation global symbols. Although this is not the proper/final solution, it does mitigate possibly symbol collisions and allow for continued superio refactorisation.
Change-Id: Iaefb25d77512503050cb38313ca90855ebb538ad Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/mainboard/advansus/a785e-i/romstage.c | 7 +++-- src/mainboard/avalue/eax-785e/romstage.c | 7 +++-- src/mainboard/kontron/986lcd-m/romstage.c | 14 ++++++++++ src/mainboard/msi/ms6178/romstage.c | 5 ++-- src/mainboard/pcengines/alix1c/romstage.c | 5 ++-- src/mainboard/supermicro/h8dme/romstage.c | 6 ++-- src/mainboard/supermicro/h8dmr/romstage.c | 8 +++--- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 6 ++-- src/mainboard/supermicro/h8qme_fam10/romstage.c | 22 ++++++++++++--- src/mainboard/supermicro/x6dai_g/romstage.c | 2 +- src/mainboard/supermicro/x6dhe_g/romstage.c | 2 +- src/mainboard/supermicro/x6dhr_ig/romstage.c | 2 +- src/mainboard/supermicro/x6dhr_ig2/romstage.c | 2 +- src/mainboard/winent/pl6064/romstage.c | 5 ++-- src/superio/winbond/w83627hf/Makefile.inc | 2 +- src/superio/winbond/w83627hf/early_init.c | 37 ++++++++++++++++++------- src/superio/winbond/w83627hf/early_serial.c | 14 ++++++++++ src/superio/winbond/w83627hf/w83627hf.h | 14 ++++------ 18 files changed, 113 insertions(+), 47 deletions(-)
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 490d146..2402798 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -41,7 +41,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -50,6 +51,8 @@ #include <southbridge/amd/cimx/sb800/smbus.h> #include "northbridge/amd/amdfam10/debug.c"
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -100,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb800_clk_output_48Mhz();
w83627hf_set_clksel_48(PNP_DEV(0x2e, 0)); - w83627hf_enable_serial(0, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); printk(BIOS_DEBUG, "\n"); diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 69cefd9..f6a10dc 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -41,7 +41,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -50,6 +51,8 @@ #include <southbridge/amd/cimx/sb800/smbus.h> #include "northbridge/amd/amdfam10/debug.c"
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -100,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb800_clk_output_48Mhz();
w83627hf_set_clksel_48(PNP_DEV(CONFIG_SIO_PORT, 0)); - w83627hf_enable_serial(0, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); printk(BIOS_DEBUG, "\n"); diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 9126889..ff02f99 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -76,6 +76,20 @@ static void ich7_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); }
+/* TODO: superio code should really not be in mainboard */ +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + /* This box has two superios, so enabling serial becomes slightly excessive. * We disable a lot of stuff to make sure that there are no conflicts between * the two. Also set up the GPIOs from the beginning. This is the "no schematic diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c index 518944f..fa78a82 100644 --- a/src/mainboard/msi/ms6178/romstage.c +++ b/src/mainboard/msi/ms6178/romstage.c @@ -25,7 +25,8 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/bist.h" #include "southbridge/intel/i82801ax/i82801ax.h" @@ -38,7 +39,7 @@ void main(unsigned long bist) { w83627hf_set_clksel_48(DUMMY_DEV); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); enable_smbus(); diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 1c4ae09..204f0bd 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -39,7 +39,8 @@ static void cs5536_enable_smbus(void) { }
#include "southbridge/amd/cs5536/early_setup.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h>
/* The part is a Hynix hy5du121622ctp-d43. * @@ -121,7 +122,7 @@ void main(unsigned long bist) * It is counting on some early MSR setup for the CS5536. */ cs5536_disable_internal_uart(); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init();
/* Halt if there was a built in self test failure */ diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index df5e2c8..47f5806 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -33,8 +33,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/winbond/w83627hf/early_serial.c" -#include "superio/winbond/w83627hf/early_init.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -186,7 +186,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
w83627hf_set_clksel_48(DUMMY_DEV); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 8ed7e6d..7d1f834 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -36,8 +36,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/winbond/w83627hf/early_serial.c" -#include "superio/winbond/w83627hf/early_init.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -114,8 +114,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- w83627hf_set_clksel_48(DUMMY_DEV); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_set_clksel_48(DUMMY_DEV); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 3f6ea70..cd185f3 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -39,8 +39,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" -#include "superio/winbond/w83627hf/early_serial.c" -#include "superio/winbond/w83627hf/early_init.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -122,7 +122,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32);
w83627hf_set_clksel_48(DUMMY_DEV); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index cca464c..9898a25 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -39,8 +39,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" -#include "superio/winbond/w83627hf/early_serial.c" -#include "superio/winbond/w83627hf/early_init.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -114,6 +114,20 @@ static const u8 spd_addr[] = { #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2) #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
+/* TODO: superio code should really not be in mainboard */ +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + static void write_GPIO(void) { pnp_enter_ext_func_mode(GPIO1_DEV); @@ -172,8 +186,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x32);
- w83627hf_set_clksel_48(DUMMY_DEV); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_set_clksel_48(DUMMY_DEV); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); write_GPIO(); diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index f57adaf..c998466 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -9,13 +9,13 @@ #include "lib/delay.c" #include "southbridge/intel/esb6300/early_smbus.c" #include "northbridge/intel/e7525/raminit.h" -#include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "debug.c" #include "watchdog.c" #include "southbridge/intel/esb6300/reset.c" #include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/intel/e7525/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 071bb35..b1c3cfa 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -9,13 +9,13 @@ #include "lib/delay.c" #include "southbridge/intel/esb6300/early_smbus.c" #include "northbridge/intel/e7520/raminit.h" -#include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "debug.c" #include "watchdog.c" #include "southbridge/intel/esb6300/reset.c" #include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 9c61d60..2dc96c1 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -7,13 +7,13 @@ #include <console/console.h> #include "southbridge/intel/i82801ex/early_smbus.c" #include "northbridge/intel/e7520/raminit.h" -#include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "debug.c" #include "watchdog.c" #include "southbridge/intel/i82801ex/reset.c" #include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index 4690a0c..0f2a644 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -7,13 +7,13 @@ #include <console/console.h> #include "southbridge/intel/i82801ex/early_smbus.c" #include "northbridge/intel/e7520/raminit.h" -#include "superio/winbond/w83627hf/w83627hf.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "debug.c" #include "watchdog.c" #include "southbridge/intel/i82801ex/reset.c" #include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index 124183c..6a38355 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -34,7 +34,8 @@ #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/lx/raminit.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -66,7 +67,7 @@ void main(unsigned long bist) * early MSR setup for CS5536. */ w83627hf_set_clksel_48(SERIAL_DEV); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init();
/* Halt if there was a built in self test failure */ diff --git a/src/superio/winbond/w83627hf/Makefile.inc b/src/superio/winbond/w83627hf/Makefile.inc index be5ec48..45c8c9c 100644 --- a/src/superio/winbond/w83627hf/Makefile.inc +++ b/src/superio/winbond/w83627hf/Makefile.inc @@ -20,5 +20,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
+romstage-$(CONFIG_SUPERIO_WINBOND_W83627HF) += early_init.c ramstage-$(CONFIG_SUPERIO_WINBOND_W83627HF) += superio.c - diff --git a/src/superio/winbond/w83627hf/early_init.c b/src/superio/winbond/w83627hf/early_init.c index 66b4098..db616ae 100644 --- a/src/superio/winbond/w83627hf/early_init.c +++ b/src/superio/winbond/w83627hf/early_init.c @@ -2,8 +2,9 @@ * This file is part of the coreboot project. * * Copyright (C) 2000 AG Electronics Ltd. - * Copyright 2003-2004 Linux Networx - * Copyright 2004 Tyan + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan + * Copyright (C) 2010 Win Enterprises (anishp@win-ent.com) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,18 +22,34 @@ */
#include <arch/io.h> +#include <device/pnp.h> #include "w83627hf.h"
-void w83627hf_disable_dev(device_t dev) +static void pnp_enter_ext_func_mode(device_t dev) { - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); }
-void w83627hf_enable_dev(device_t dev, u16 iobase) +static void pnp_exit_ext_func_mode(device_t dev) { - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); + u16 port = dev >> 8; + outb(0xaa, port); +} + +/* + * We duplicate this function, for non-ROMCC boards, from early_serial.c to + * work around a limitation of ROMCC where we can no make early_serial.c into + * link-time symbols and #include early_serial.c. + */ +void w83627hf_set_clksel_48(device_t dev) +{ + u8 reg8; + + pnp_enter_ext_func_mode(dev); + reg8 = pnp_read_config(dev, 0x24); + reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */ + pnp_write_config(dev, 0x24, reg8); + pnp_exit_ext_func_mode(dev); } diff --git a/src/superio/winbond/w83627hf/early_serial.c b/src/superio/winbond/w83627hf/early_serial.c index db2827b..2faf1ba 100644 --- a/src/superio/winbond/w83627hf/early_serial.c +++ b/src/superio/winbond/w83627hf/early_serial.c @@ -22,6 +22,8 @@ */
#include <arch/io.h> +/* arch/io.h has special inlined versions of device/pnp.h for romcc to compile */ +/* #include <device/pnp.h> */ #include "w83627hf.h"
static void pnp_enter_ext_func_mode(device_t dev) @@ -37,6 +39,18 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, port); }
+/* + * FIXME: The following ROMCC boards are blocking the removal this superio's + * model specific w83627hf_enable_serial() symbol. + * + * mainboard/supermicro/x6dai_g + * mainboard/supermicro/x6dhe_g + * mainboard/supermicro/x6dhr_ig + * mainboard/supermicro/x6dhr_ig2 + * + * XXX: ROMCC - everything is inlined, no forwarding function prototypes + * declarations are accepted. + */ void w83627hf_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); diff --git a/src/superio/winbond/w83627hf/w83627hf.h b/src/superio/winbond/w83627hf/w83627hf.h index 468cb55..bf7186e 100644 --- a/src/superio/winbond/w83627hf/w83627hf.h +++ b/src/superio/winbond/w83627hf/w83627hf.h @@ -20,8 +20,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#ifndef SUPERIO_WINBOND_W83627HF_W83627HF_H -#define SUPERIO_WINBOND_W83627HF_W83627HF_H +#ifndef SUPERIO_WINBOND_W83627HF_H +#define SUPERIO_WINBOND_W83627HF_H
#define W83627HF_FDC 0 /* Floppy */ #define W83627HF_PP 1 /* Parallel port */ @@ -113,11 +113,9 @@ #define W83627HF_XSCNF 0x15 #define W83627HF_XWBCNF 0x16
-#if defined(__PRE_RAM__) -void w83627hf_disable_dev(device_t dev); -void w83627hf_enable_dev(device_t dev, u16 iobase); -void w83627hf_enable_serial(device_t dev, u16 iobase); +#include <arch/io.h> + void w83627hf_set_clksel_48(device_t dev); -#endif +void w83627hf_enable_serial(device_t dev, u16 iobase);
-#endif +#endif /* SUPERIO_WINBOND_W83627HF_H */
-
Edward O'Callaghan