Change in coreboot[master]: mb/*/chromeos.c: Remove some ENV_RAMSTAGE and __SIMPLE_DEVICE__
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34519 )
Change subject: mb/*/chromeos.c: Remove some ENV_RAMSTAGE and __SIMPLE_DEVICE__ ......................................................................
mb/*/chromeos.c: Remove some ENV_RAMSTAGE and __SIMPLE_DEVICE__
Use explicit simple PCI config accessors here.
Change-Id: Ifa3814fdd7795479ca5fdbfc4deb3fe8db9805f3 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/dragonegg/chromeos.c M src/mainboard/google/eve/chromeos.c M src/mainboard/google/fizz/chromeos.c M src/mainboard/google/glados/chromeos.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/sarien/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/cannonlake_rvp/chromeos.c M src/mainboard/intel/coffeelake_rvp/chromeos.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kunimitsu/chromeos.c M src/mainboard/intel/strago/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/chromeos.c 22 files changed, 44 insertions(+), 158 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/34519/1
diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index e695ab5..1039707 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -15,6 +15,7 @@
#include <device/pci_ops.h> #include <bootmode.h> +#include <boot/coreboot_tables.h> #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> @@ -27,9 +28,6 @@ #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -43,36 +41,23 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_write_protect_state(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; }
int get_recovery_mode_switch(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; }
void init_bootmode_straps(void) { u32 flags = 0; -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif
/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ if (get_gpio(GPIO_SPI_WP)) @@ -84,7 +69,7 @@
/* Developer: Virtual */
- pci_write_config32(dev, SATA_SP, flags); + pci_s_write_config32(dev, SATA_SP, flags); }
static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 7f72ad2..2825aae 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <string.h> #include <bootmode.h> +#include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> @@ -30,9 +31,6 @@ #define DEVMODE_GPIO 54 #define FORCE_RECOVERY_MODE 0
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -53,7 +51,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_write_protect_state(void) { diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 5d5bc55..154b913 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#include <boot/coreboot_tables.h> #include <device/mmio.h> #include <gpio.h> #include <soc/gpio.h> @@ -25,9 +26,6 @@
#define WP_GPIO GP_E_22
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - #define ACTIVE_LOW 0 #define ACTIVE_HIGH 1
@@ -41,7 +39,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_write_protect_state(void) { diff --git a/src/mainboard/google/dragonegg/chromeos.c b/src/mainboard/google/dragonegg/chromeos.c index 7132b04..3b69bff 100644 --- a/src/mainboard/google/dragonegg/chromeos.c +++ b/src/mainboard/google/dragonegg/chromeos.c @@ -15,15 +15,13 @@
#include <arch/acpi.h> #include <baseboard/variants.h> +#include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
#include <variant/gpio.h>
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -36,7 +34,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_write_protect_state(void) { diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index 8c276e9..9a1dd04 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -14,15 +14,13 @@ * GNU General Public License for more details. */
+#include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
#include "gpio.h"
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -35,7 +33,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_write_protect_state(void) { diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index 31887c5..25c52a5 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <boot/coreboot_tables.h> #include <gpio.h> #include <baseboard/variants.h> #include <soc/gpio.h> @@ -20,9 +21,6 @@
#include <variant/gpio.h>
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -35,7 +33,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_write_protect_state(void) { diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index b6029dd..c89a9a8 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -14,14 +14,12 @@ * GNU General Public License for more details. */
+#include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include <variant/gpio.h>
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -34,7 +32,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_write_protect_state(void) { diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index 2b72cae..f2db756 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> @@ -28,9 +29,6 @@ #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -44,36 +42,23 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_write_protect_state(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; }
int get_recovery_mode_switch(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; }
void init_bootmode_straps(void) { u32 flags = 0; -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif
/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ if (get_gpio(GPIO_SPI_WP)) @@ -85,7 +70,7 @@
/* Developer: Virtual */
- pci_write_config32(dev, SATA_SP, flags); + pci_s_write_config32(dev, SATA_SP, flags); }
static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 095d504..4adcdb6 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <string.h> #include <bootmode.h> +#include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> @@ -26,14 +27,10 @@ #include <vendorcode/google/chromeos/chromeos.h> #include "ec.h"
- -#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { - struct device *dev = pcidev_on_root(0x1f, 0); - u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1);
struct lb_gpio chromeos_gpios[] = { /* Write Protect: GPIO70 active high */ @@ -51,7 +48,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_lid_switch(void) { diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index 3879732..84b0031 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -15,14 +15,13 @@
#include <arch/acpi.h> #include <baseboard/variants.h> +#include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
#include <variant/gpio.h>
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h>
void fill_lb_gpios(struct lb_gpios *gpios) { @@ -36,7 +35,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_write_protect_state(void) { diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 7aaf401..8f940ea 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -120,8 +120,7 @@
void mainboard_prepare_cr50_reset(void) { -#if ENV_RAMSTAGE /* Ensure system powers up after CR50 reset */ - pmc_set_afterg3(MAINBOARD_POWER_STATE_ON); -#endif + if (ENV_RAMSTAGE) + pmc_set_afterg3(MAINBOARD_POWER_STATE_ON); } diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 60c7a09..ff247da 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -15,6 +15,7 @@
#include <string.h> #include <bootmode.h> +#include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/device.h> @@ -26,9 +27,6 @@ #include "ec.h" #include <ec/quanta/it8518/ec.h>
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -51,7 +49,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_write_protect_state(void) { @@ -74,16 +71,14 @@ */ int get_recovery_mode_switch(void) { -#ifdef __PRE_RAM__ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); -#else +#ifndef __PRE_RAM__ static int ec_in_rec_mode = 0; static int ec_rec_flag_good = 0; - struct device *dev = pcidev_on_root(0x1f, 0); #endif + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u8 reg8 = pci_s_read_config8(dev, GEN_PMCON_3);
u8 ec_status = ec_read(EC_STATUS_REG); - u8 reg8 = pci_read_config8(dev, GEN_PMCON_3);
printk(BIOS_SPEW,"%s: EC status:%#x RTC_BAT: %x\n", __func__, ec_status, reg8 & RTC_BATTERY_DEAD); diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 6561927..6048620 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -15,6 +15,7 @@
#include <string.h> #include <bootmode.h> +#include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> @@ -22,9 +23,6 @@ #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -45,7 +43,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_recovery_mode_switch(void) { diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c index 44254bc..0440994 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.c +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.c @@ -15,14 +15,12 @@
#include <arch/acpi.h> #include <baseboard/variants.h> +#include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -33,7 +31,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_lid_switch(void) { diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index a581217..e7094d7 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -15,13 +15,11 @@
#include <arch/acpi.h> #include <baseboard/variants.h> +#include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -32,7 +30,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_lid_switch(void) { diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 699141f..74fe20f 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -15,6 +15,7 @@
#include <string.h> #include <bootmode.h> +#include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> @@ -22,9 +23,6 @@ #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -45,7 +43,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_recovery_mode_switch(void) { diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index ce8e548..785fe4a 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -15,14 +15,12 @@
#include <arch/acpi.h> #include <baseboard/variants.h> +#include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -33,7 +31,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_lid_switch(void) { diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index ff93d27..29f05c9 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#include <boot/coreboot_tables.h> #include <device/device.h> #include <device/pci.h> #include <gpio.h> @@ -24,9 +25,6 @@ #include "gpio.h" #include "ec.h"
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -37,7 +35,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_lid_switch(void) { diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 6422488..3f3dd40 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -14,15 +14,12 @@ * GNU General Public License for more details. */
+#include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> - #include "gpio.h"
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -35,7 +32,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_write_protect_state(void) { diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index df36b38..540ba6a 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -14,14 +14,12 @@ * GNU General Public License for more details. */
+#include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
#define WP_GPIO GP_E_22
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - #define ACTIVE_LOW 0 #define ACTIVE_HIGH 1
@@ -35,7 +33,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_write_protect_state(void) { diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 6760f03..9e02d9a 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -15,6 +15,7 @@
#include <string.h> #include <bootmode.h> +#include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> @@ -29,15 +30,13 @@ #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> #include "ec.h" #include <ec/smsc/mec1308/ec.h>
void fill_lb_gpios(struct lb_gpios *gpios) { - struct device *dev = pcidev_on_root(0x1f, 0); - u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); u8 lid = ec_read(0x83);
struct lb_gpio chromeos_gpios[] = { @@ -60,36 +59,23 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_write_protect_state(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; }
int get_recovery_mode_switch(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; }
void init_bootmode_straps(void) { u32 flags = 0; -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif
/* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */ if (get_gpio(GPIO_SPI_WP)) @@ -98,7 +84,7 @@ if (!get_gpio(GPIO_REC_MODE)) flags |= (1 << FLAG_REC_MODE);
- pci_write_config32(dev, SATA_SP, flags); + pci_s_write_config32(dev, SATA_SP, flags); }
static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 9ec4218..f316b22 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -15,6 +15,7 @@
#include <string.h> #include <bootmode.h> +#include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> @@ -28,13 +29,10 @@ #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { - struct device *dev = pcidev_on_root(0x1f, 0); - u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1);
struct lb_gpio chromeos_gpios[] = { /* Write Protect: GPIO68 = CHP3_SPI_WP */ @@ -57,36 +55,23 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_write_protect_state(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; }
int get_recovery_mode_switch(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; }
void init_bootmode_straps(void) { u32 flags = 0; -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif
/* Write Protect: GPIO68 = CHP3_SPI_WP, active high */ if (get_gpio(GPIO_SPI_WP)) @@ -95,7 +80,7 @@ if (!get_gpio(GPIO_REC_MODE)) flags |= (1 << FLAG_REC_MODE);
- pci_write_config32(dev, SATA_SP, flags); + pci_s_write_config32(dev, SATA_SP, flags); }
static const struct cros_gpio cros_gpios[] = {
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34519 )
Change subject: mb/*/chromeos.c: Remove some ENV_RAMSTAGE and __SIMPLE_DEVICE__ ......................................................................
Patch Set 1: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34519 )
Change subject: mb/*/chromeos.c: Remove some ENV_RAMSTAGE and __SIMPLE_DEVICE__ ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34519 )
Change subject: mb/*/chromeos.c: Remove some ENV_RAMSTAGE and __SIMPLE_DEVICE__ ......................................................................
mb/*/chromeos.c: Remove some ENV_RAMSTAGE and __SIMPLE_DEVICE__
Use explicit simple PCI config accessors here.
Change-Id: Ifa3814fdd7795479ca5fdbfc4deb3fe8db9805f3 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34519 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/dragonegg/chromeos.c M src/mainboard/google/eve/chromeos.c M src/mainboard/google/fizz/chromeos.c M src/mainboard/google/glados/chromeos.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/poppy/chromeos.c M src/mainboard/google/sarien/chromeos.c M src/mainboard/google/stout/chromeos.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/cannonlake_rvp/chromeos.c M src/mainboard/intel/coffeelake_rvp/chromeos.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/icelake_rvp/chromeos.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kunimitsu/chromeos.c M src/mainboard/intel/strago/chromeos.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/chromeos.c 22 files changed, 44 insertions(+), 158 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index e695ab5..1039707 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -15,6 +15,7 @@
#include <device/pci_ops.h> #include <bootmode.h> +#include <boot/coreboot_tables.h> #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> @@ -27,9 +28,6 @@ #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -43,36 +41,23 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_write_protect_state(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; }
int get_recovery_mode_switch(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; }
void init_bootmode_straps(void) { u32 flags = 0; -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif
/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ if (get_gpio(GPIO_SPI_WP)) @@ -84,7 +69,7 @@
/* Developer: Virtual */
- pci_write_config32(dev, SATA_SP, flags); + pci_s_write_config32(dev, SATA_SP, flags); }
static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 7f72ad2..2825aae 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <string.h> #include <bootmode.h> +#include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> @@ -30,9 +31,6 @@ #define DEVMODE_GPIO 54 #define FORCE_RECOVERY_MODE 0
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -53,7 +51,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_write_protect_state(void) { diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 5d5bc55..154b913 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#include <boot/coreboot_tables.h> #include <device/mmio.h> #include <gpio.h> #include <soc/gpio.h> @@ -25,9 +26,6 @@
#define WP_GPIO GP_E_22
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - #define ACTIVE_LOW 0 #define ACTIVE_HIGH 1
@@ -41,7 +39,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_write_protect_state(void) { diff --git a/src/mainboard/google/dragonegg/chromeos.c b/src/mainboard/google/dragonegg/chromeos.c index 7132b04..3b69bff 100644 --- a/src/mainboard/google/dragonegg/chromeos.c +++ b/src/mainboard/google/dragonegg/chromeos.c @@ -15,15 +15,13 @@
#include <arch/acpi.h> #include <baseboard/variants.h> +#include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
#include <variant/gpio.h>
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -36,7 +34,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_write_protect_state(void) { diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index 8c276e9..9a1dd04 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -14,15 +14,13 @@ * GNU General Public License for more details. */
+#include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
#include "gpio.h"
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -35,7 +33,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_write_protect_state(void) { diff --git a/src/mainboard/google/fizz/chromeos.c b/src/mainboard/google/fizz/chromeos.c index 31887c5..25c52a5 100644 --- a/src/mainboard/google/fizz/chromeos.c +++ b/src/mainboard/google/fizz/chromeos.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <boot/coreboot_tables.h> #include <gpio.h> #include <baseboard/variants.h> #include <soc/gpio.h> @@ -20,9 +21,6 @@
#include <variant/gpio.h>
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -35,7 +33,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_write_protect_state(void) { diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index b6029dd..c89a9a8 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -14,14 +14,12 @@ * GNU General Public License for more details. */
+#include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include <variant/gpio.h>
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -34,7 +32,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_write_protect_state(void) { diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index 2b72cae..f2db756 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> @@ -28,9 +29,6 @@ #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -44,36 +42,23 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_write_protect_state(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; }
int get_recovery_mode_switch(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; }
void init_bootmode_straps(void) { u32 flags = 0; -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif
/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ if (get_gpio(GPIO_SPI_WP)) @@ -85,7 +70,7 @@
/* Developer: Virtual */
- pci_write_config32(dev, SATA_SP, flags); + pci_s_write_config32(dev, SATA_SP, flags); }
static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 095d504..4adcdb6 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <string.h> #include <bootmode.h> +#include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> @@ -26,14 +27,10 @@ #include <vendorcode/google/chromeos/chromeos.h> #include "ec.h"
- -#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { - struct device *dev = pcidev_on_root(0x1f, 0); - u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1);
struct lb_gpio chromeos_gpios[] = { /* Write Protect: GPIO70 active high */ @@ -51,7 +48,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_lid_switch(void) { diff --git a/src/mainboard/google/poppy/chromeos.c b/src/mainboard/google/poppy/chromeos.c index 3879732..84b0031 100644 --- a/src/mainboard/google/poppy/chromeos.c +++ b/src/mainboard/google/poppy/chromeos.c @@ -15,14 +15,13 @@
#include <arch/acpi.h> #include <baseboard/variants.h> +#include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
#include <variant/gpio.h>
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h>
void fill_lb_gpios(struct lb_gpios *gpios) { @@ -36,7 +35,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_write_protect_state(void) { diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 7aaf401..8f940ea 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -120,8 +120,7 @@
void mainboard_prepare_cr50_reset(void) { -#if ENV_RAMSTAGE /* Ensure system powers up after CR50 reset */ - pmc_set_afterg3(MAINBOARD_POWER_STATE_ON); -#endif + if (ENV_RAMSTAGE) + pmc_set_afterg3(MAINBOARD_POWER_STATE_ON); } diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 60c7a09..ff247da 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -15,6 +15,7 @@
#include <string.h> #include <bootmode.h> +#include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/device.h> @@ -26,9 +27,6 @@ #include "ec.h" #include <ec/quanta/it8518/ec.h>
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -51,7 +49,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_write_protect_state(void) { @@ -74,16 +71,14 @@ */ int get_recovery_mode_switch(void) { -#ifdef __PRE_RAM__ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); -#else +#ifndef __PRE_RAM__ static int ec_in_rec_mode = 0; static int ec_rec_flag_good = 0; - struct device *dev = pcidev_on_root(0x1f, 0); #endif + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u8 reg8 = pci_s_read_config8(dev, GEN_PMCON_3);
u8 ec_status = ec_read(EC_STATUS_REG); - u8 reg8 = pci_read_config8(dev, GEN_PMCON_3);
printk(BIOS_SPEW,"%s: EC status:%#x RTC_BAT: %x\n", __func__, ec_status, reg8 & RTC_BATTERY_DEAD); diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 6561927..6048620 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -15,6 +15,7 @@
#include <string.h> #include <bootmode.h> +#include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> @@ -22,9 +23,6 @@ #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -45,7 +43,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_recovery_mode_switch(void) { diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c index 44254bc..0440994 100644 --- a/src/mainboard/intel/cannonlake_rvp/chromeos.c +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.c @@ -15,14 +15,12 @@
#include <arch/acpi.h> #include <baseboard/variants.h> +#include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -33,7 +31,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_lid_switch(void) { diff --git a/src/mainboard/intel/coffeelake_rvp/chromeos.c b/src/mainboard/intel/coffeelake_rvp/chromeos.c index a581217..e7094d7 100644 --- a/src/mainboard/intel/coffeelake_rvp/chromeos.c +++ b/src/mainboard/intel/coffeelake_rvp/chromeos.c @@ -15,13 +15,11 @@
#include <arch/acpi.h> #include <baseboard/variants.h> +#include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -32,7 +30,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_lid_switch(void) { diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 699141f..74fe20f 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -15,6 +15,7 @@
#include <string.h> #include <bootmode.h> +#include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> @@ -22,9 +23,6 @@ #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -45,7 +43,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_recovery_mode_switch(void) { diff --git a/src/mainboard/intel/icelake_rvp/chromeos.c b/src/mainboard/intel/icelake_rvp/chromeos.c index ce8e548..785fe4a 100644 --- a/src/mainboard/intel/icelake_rvp/chromeos.c +++ b/src/mainboard/intel/icelake_rvp/chromeos.c @@ -15,14 +15,12 @@
#include <arch/acpi.h> #include <baseboard/variants.h> +#include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -33,7 +31,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_lid_switch(void) { diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index ff93d27..29f05c9 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#include <boot/coreboot_tables.h> #include <device/device.h> #include <device/pci.h> #include <gpio.h> @@ -24,9 +25,6 @@ #include "gpio.h" #include "ec.h"
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -37,7 +35,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_lid_switch(void) { diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 6422488..3f3dd40 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -14,15 +14,12 @@ * GNU General Public License for more details. */
+#include <boot/coreboot_tables.h> #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> - #include "gpio.h"
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -35,7 +32,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_write_protect_state(void) { diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index df36b38..540ba6a 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -14,14 +14,12 @@ * GNU General Public License for more details. */
+#include <boot/coreboot_tables.h> #include <gpio.h> #include <vendorcode/google/chromeos/chromeos.h>
#define WP_GPIO GP_E_22
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - #define ACTIVE_LOW 0 #define ACTIVE_HIGH 1
@@ -35,7 +33,6 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif /* ENV_RAMSTAGE */
int get_write_protect_state(void) { diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 6760f03..9e02d9a 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -15,6 +15,7 @@
#include <string.h> #include <bootmode.h> +#include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> @@ -29,15 +30,13 @@ #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> #include "ec.h" #include <ec/smsc/mec1308/ec.h>
void fill_lb_gpios(struct lb_gpios *gpios) { - struct device *dev = pcidev_on_root(0x1f, 0); - u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); u8 lid = ec_read(0x83);
struct lb_gpio chromeos_gpios[] = { @@ -60,36 +59,23 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_write_protect_state(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; }
int get_recovery_mode_switch(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; }
void init_bootmode_straps(void) { u32 flags = 0; -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif
/* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */ if (get_gpio(GPIO_SPI_WP)) @@ -98,7 +84,7 @@ if (!get_gpio(GPIO_REC_MODE)) flags |= (1 << FLAG_REC_MODE);
- pci_write_config32(dev, SATA_SP, flags); + pci_s_write_config32(dev, SATA_SP, flags); }
static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 9ec4218..f316b22 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -15,6 +15,7 @@
#include <string.h> #include <bootmode.h> +#include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> @@ -28,13 +29,10 @@ #define FLAG_SPI_WP 0 #define FLAG_REC_MODE 1
-#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - void fill_lb_gpios(struct lb_gpios *gpios) { - struct device *dev = pcidev_on_root(0x1f, 0); - u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1);
struct lb_gpio chromeos_gpios[] = { /* Write Protect: GPIO68 = CHP3_SPI_WP */ @@ -57,36 +55,23 @@ }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -#endif
int get_write_protect_state(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; }
int get_recovery_mode_switch(void) { -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif - return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; + return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; }
void init_bootmode_straps(void) { u32 flags = 0; -#ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); -#else - struct device *dev = pcidev_on_root(0x1f, 2); -#endif
/* Write Protect: GPIO68 = CHP3_SPI_WP, active high */ if (get_gpio(GPIO_SPI_WP)) @@ -95,7 +80,7 @@ if (!get_gpio(GPIO_REC_MODE)) flags |= (1 << FLAG_REC_MODE);
- pci_write_config32(dev, SATA_SP, flags); + pci_s_write_config32(dev, SATA_SP, flags); }
static const struct cros_gpio cros_gpios[] = {
-
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