Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42695 )
Change subject: nb/intel/ironlake: Remove unused structs ......................................................................
nb/intel/ironlake: Remove unused structs
These were copied from gm45, but are not used. Drop them.
Change-Id: I85ca37516272a2c1af88a65df2682e92d7579050 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/ironlake/ironlake.h 1 file changed, 0 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/42695/1
diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 93d55a9..53efced 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -3,38 +3,6 @@ #ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ #define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__
-#ifndef __ASSEMBLER__ - -typedef struct { - unsigned int CAS; - unsigned int tRAS; - unsigned int tRP; - unsigned int tRCD; - unsigned int tRFC; - unsigned int tWR; - unsigned int tRD; - unsigned int tRRD; - unsigned int tFAW; - unsigned int tWL; -} timings_t; - -/* The setup is one DIMM per channel, so there's no need to find a - common timing setup between multiple chips (but chip and controller - still need to be coordinated */ -typedef struct { - int txt_enabled; - int cores; - int max_ddr2_mhz; - int max_ddr3_mt; - int max_fsb_mhz; - int max_render_mhz; - - int spd_type; - timings_t selected_timings; -} sysinfo_t; - -#endif - #define DEFAULT_HECIBAR ((u8 *)0xfed17000)
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42695 )
Change subject: nb/intel/ironlake: Remove unused structs ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42695 )
Change subject: nb/intel/ironlake: Remove unused structs ......................................................................
nb/intel/ironlake: Remove unused structs
These were copied from gm45, but are not used. Drop them.
Change-Id: I85ca37516272a2c1af88a65df2682e92d7579050 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42695 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Georgi pgeorgi@google.com --- M src/northbridge/intel/ironlake/ironlake.h 1 file changed, 0 insertions(+), 32 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 93d55a9..53efced 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -3,38 +3,6 @@ #ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ #define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__
-#ifndef __ASSEMBLER__ - -typedef struct { - unsigned int CAS; - unsigned int tRAS; - unsigned int tRP; - unsigned int tRCD; - unsigned int tRFC; - unsigned int tWR; - unsigned int tRD; - unsigned int tRRD; - unsigned int tFAW; - unsigned int tWL; -} timings_t; - -/* The setup is one DIMM per channel, so there's no need to find a - common timing setup between multiple chips (but chip and controller - still need to be coordinated */ -typedef struct { - int txt_enabled; - int cores; - int max_ddr2_mhz; - int max_ddr3_mt; - int max_fsb_mhz; - int max_render_mhz; - - int spd_type; - timings_t selected_timings; -} sysinfo_t; - -#endif - #define DEFAULT_HECIBAR ((u8 *)0xfed17000)
-
Angel Pons (Code Review) -
Patrick Georgi (Code Review)