Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50446 )
Change subject: soc/amd/common/blocks/lpc: Remove common SPI registers ......................................................................
soc/amd/common/blocks/lpc: Remove common SPI registers
Use the SoC versions instead.
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ia0b8129b165f8a2e6be6706ab2e3f2d39e1025a0 --- M src/soc/amd/common/block/include/amdblocks/lpc.h M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/common/block/lpc/lpc_util.c M src/soc/amd/common/block/spi/fch_spi.c 4 files changed, 4 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/50446/1
diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index fbedb71..4e2660b 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -113,15 +113,6 @@
#define LPC_WIDEIO2_GENERIC_PORT 0x90
-#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 -#define SPI_BASE_ALIGNMENT BIT(6) -#define SPI_BASE_RESERVED (BIT(4) | BIT(5)) -#define ROUTE_TPM_2_SPI BIT(3) -#define SPI_ABORT_ENABLE BIT(2) -#define SPI_ROM_ENABLE BIT(1) -#define SPI_ROM_ALT_ENABLE BIT(0) -#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) - /* LPC register 0xb8 is DWORD, here there are definitions for byte access. For example, bits 31-24 are accessed through byte access at register 0xbb. */ diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 7f3bea0..d68814b 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -16,8 +16,9 @@ #include <amdblocks/espi.h> #include <amdblocks/lpc.h> #include <soc/acpi.h> -#include <soc/southbridge.h> #include <soc/iomap.h> +#include <soc/lpc.h> +#include <soc/southbridge.h>
/* Most systems should have already enabled the bridge */ void __weak soc_late_lpc_bridge_enable(void) { } diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index eb129dc..fb231dd 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -8,6 +8,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/lpc.h> #include <soc/iomap.h> +#include <soc/lpc.h> #include <soc/southbridge.h>
/* The LPC-ISA bridge is always at D14F3 */ diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index c39147a..a644d27 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -6,6 +6,7 @@ #include <arch/mmio.h> #include <console/console.h> #include <soc/iomap.h> +#include <soc/lpc.h> #include <stdint.h>
static void fch_spi_set_spi100(int norm, int fast, int alt, int tpm)
-
Raul Rangel (Code Review)