Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/29421
Change subject: mediatek/mt8183: Add PMIC wrapper support ......................................................................
mediatek/mt8183: Add PMIC wrapper support
BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui
Change-Id: Idbdb15f11227ded3f5d18fe6504c8c646973b733 Signed-off-by: Hsin-Hsiung Wang hsin-hsiung.wang@mediatek.com --- M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/pmic_wrap.h A src/soc/mediatek/mt8183/pmic_wrap.c 4 files changed, 883 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/29421/1
diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 5650465..e8efe90 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -34,6 +34,7 @@ ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c +ramstage-y += ../common/pmic_wrap.c pmic_wrap.c ramstage-y += soc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += ../common/timer.c diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index 1ba9cc8..78c6cf4 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -29,6 +29,7 @@ RGU_BASE = IO_PHYS + 0x00007000, GPT_BASE = IO_PHYS + 0x00008000, APMIXED_BASE = IO_PHYS + 0x0000C000, + PWRAP_BASE = IO_PHYS + 0x0000D000, EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, DRAMC_CH_BASE = IO_PHYS + 0x00228000, diff --git a/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h new file mode 100644 index 0000000..a995038 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h @@ -0,0 +1,570 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MEDIATEK_MT8183_PMIC_WRAP_H__ +#define __SOC_MEDIATEK_MT8183_PMIC_WRAP_H__ + +#include <soc/addressmap.h> +#include <soc/pmic_wrap_common.h> +#include <types.h> + +struct mt8183_pwrap_regs { + u32 mux_sel; + u32 wrap_en; + u32 dio_en; + u32 si_sample_ctrl; + u32 si_sample_ctrl_ulposc; + u32 rddmy; + u32 cshext_write; + u32 cshext_read; + u32 cslext_write; + u32 cslext_read; + u32 ext_ck_write; + u32 ext_ck_read; + u32 staupd_ctrl; + u32 staupd_grpen; + u32 eint_sta0_adr; + u32 eint_sta1_adr; + u32 eint_sta; + u32 eint_clr; + u32 eint_ctrl; + u32 staupd_man_trig; + u32 staupd_sta; + u32 wrap_sta; + u32 harb_init; + u32 harb_hprio; + u32 hiprio_arb_en; + u32 harb_sta0; + u32 harb_sta1; + u32 harb_sta2; + u32 man_en; + u32 man_cmd; + u32 man_rdata; + u32 man_vldclr; + u32 wacs0_en; + u32 init_done0; + u32 wacs1_en; + u32 init_done1; + u32 wacs2_en; + u32 init_done2; + u32 wacs3_en; + u32 init_done3; + u32 wacs_p2p_en; + u32 init_done_p2p; + u32 wacs_md32_en; + u32 init_done_md32; + u32 int0_en; + u32 int0_flg_raw; + u32 int0_flg; + u32 int0_clr; + u32 int1_en; + u32 int1_flg_raw; + u32 int1_flg; + u32 int1_clr; + u32 sig_adr; + u32 sig_mode; + u32 sig_value; + u32 sig_errval; + u32 crc_en; + u32 timer_en; + u32 timer_sta; + u32 wdt_unit; + u32 wdt_src_en_0; + u32 wdt_src_en_1; + u32 wdt_flg_0; + u32 wdt_flg_1; + u32 debug_int_sel; + u32 dvfs_adr0; + u32 dvfs_wdata0; + u32 dvfs_adr1; + u32 dvfs_wdata1; + u32 dvfs_adr2; + u32 dvfs_wdata2; + u32 dvfs_adr3; + u32 dvfs_wdata3; + u32 dvfs_adr4; + u32 dvfs_wdata4; + u32 dvfs_adr5; + u32 dvfs_wdata5; + u32 dvfs_adr6; + u32 dvfs_wdata6; + u32 dvfs_adr7; + u32 dvfs_wdata7; + u32 dvfs_adr8; + u32 dvfs_wdata8; + u32 dvfs_adr9; + u32 dvfs_wdata9; + u32 dvfs_adr10; + u32 dvfs_wdata10; + u32 dvfs_adr11; + u32 dvfs_wdata11; + u32 dvfs_adr12; + u32 dvfs_wdata12; + u32 dvfs_adr13; + u32 dvfs_wdata13; + u32 dvfs_adr14; + u32 dvfs_wdata14; + u32 dvfs_adr15; + u32 dvfs_wdata15; + u32 dcxo_enable; + u32 dcxo_conn_adr0; + u32 dcxo_conn_wdata0; + u32 dcxo_conn_adr1; + u32 dcxo_conn_wdata1; + u32 dcxo_nfc_adr0; + u32 dcxo_nfc_wdata0; + u32 dcxo_nfc_adr1; + u32 dcxo_nfc_wdata1; + u32 spminf_sta_0; + u32 spminf_sta_1; + u32 spminf_backup_sta; + u32 scpinf_sta; + u32 cipher_key_sel; + u32 cipher_iv_sel; + u32 cipher_en; + u32 cipher_rdy; + u32 cipher_mode; + u32 cipher_swrst; + u32 dcm_en; + u32 dcm_spi_dbc_prd; + u32 dcm_dbc_prd; + u32 int_gps_auxadc_cmd_addr; + u32 int_gps_auxadc_cmd; + u32 int_gps_auxadc_rdata_addr; + u32 ext_gps_auxadc_rdata_addr; + u32 gpsinf_0_sta; + u32 gpsinf_1_sta; + u32 md_adcinf_ctrl; + u32 md_auxadc_rdata_latest_addr; + u32 md_auxadc_rdata_wp_addr; + u32 md_auxadc_rdata[32]; + u32 md_adcinf_0_sta_0; + u32 md_adcinf_0_sta_1; + u32 md_adcinf_1_sta_0; + u32 md_adcinf_1_sta_1; + u32 swrst; + u32 spm_sleep_gating_ctrl; + u32 scp_sleep_gating_ctrl; + u32 priority_user_sel_0; + u32 priority_user_sel_1; + u32 priority_user_sel_2; + u32 priority_user_sel_3; + u32 priority_user_sel_4; + u32 arbiter_out_sel_0; + u32 arbiter_out_sel_1; + u32 arbiter_out_sel_2; + u32 arbiter_out_sel_3; + u32 arbiter_out_sel_4; + u32 starv_counter_0; + u32 starv_counter_1; + u32 starv_counter_2; + u32 starv_counter_3; + u32 starv_counter_4; + u32 starv_counter_5; + u32 starv_counter_6; + u32 starv_counter_7; + u32 starv_counter_8; + u32 starv_counter_9; + u32 starv_counter_10; + u32 starv_counter_11; + u32 starv_counter_12; + u32 starv_counter_13; + u32 starv_counter_14; + u32 starv_counter_15; + u32 starv_counter_16; + u32 starv_counter_0_status; + u32 starv_counter_1_status; + u32 starv_counter_2_status; + u32 starv_counter_3_status; + u32 starv_counter_4_status; + u32 starv_counter_5_status; + u32 starv_counter_6_status; + u32 starv_counter_7_status; + u32 starv_counter_8_status; + u32 starv_counter_9_status; + u32 starv_counter_10_status; + u32 starv_counter_11_status; + u32 starv_counter_12_status; + u32 starv_counter_13_status; + u32 starv_counter_14_status; + u32 starv_counter_15_status; + u32 starv_counter_16_status; + u32 starv_counter_clr; + u32 starv_prio_status; + u32 monitor_ctrl_0; + u32 monitor_ctrl_1; + u32 monitor_ctrl_2; + u32 monitor_ctrl_3; + u32 channel_sequence_0; + u32 channel_sequence_1; + u32 channel_sequence_2; + u32 channel_sequence_3; + u32 cmd_sequence_0; + u32 cmd_sequence_1; + u32 cmd_sequence_2; + u32 cmd_sequence_3; + u32 cmd_sequence_4; + u32 cmd_sequence_5; + u32 cmd_sequence_6; + u32 cmd_sequence_7; + u32 wdata_sequence_0; + u32 wdata_sequence_1; + u32 wdata_sequence_2; + u32 wdata_sequence_3; + u32 wdata_sequence_4; + u32 wdata_sequence_5; + u32 wdata_sequence_6; + u32 wdata_sequence_7; + u32 debug_sw_driver_0; + u32 debug_sw_driver_1; + u32 debug_sw_driver_2; + u32 debug_sw_driver_3; + u32 debug_sw_driver_4; + u32 debug_sw_driver_5; + u32 bwc_options; + u32 reserved1[524]; + u32 wacs0_cmd; + u32 wacs0_rdata; + u32 wacs0_vldclr; + u32 reserved2; + u32 wacs1_cmd; + u32 wacs1_rdata; + u32 wacs1_vldclr; + u32 reserved3; + u32 wacs2_cmd; + u32 wacs2_rdata; + u32 wacs2_vldclr; + u32 reserved4; + u32 wacs3_cmd; + u32 wacs3_rdata; + u32 wacs3_vldclr; +}; + +check_member(mt8183_pwrap_regs, mux_sel, 0x0); +check_member(mt8183_pwrap_regs, wrap_en, 0x4); +check_member(mt8183_pwrap_regs, dio_en, 0x8); +check_member(mt8183_pwrap_regs, si_sample_ctrl, 0xC); +check_member(mt8183_pwrap_regs, si_sample_ctrl_ulposc, 0x10); +check_member(mt8183_pwrap_regs, rddmy, 0x14); +check_member(mt8183_pwrap_regs, cshext_write, 0x18); +check_member(mt8183_pwrap_regs, cshext_read, 0x1C); +check_member(mt8183_pwrap_regs, cslext_write, 0x20); +check_member(mt8183_pwrap_regs, cslext_read, 0x24); +check_member(mt8183_pwrap_regs, ext_ck_write, 0x28); +check_member(mt8183_pwrap_regs, ext_ck_read, 0x2C); +check_member(mt8183_pwrap_regs, staupd_ctrl, 0x30); +check_member(mt8183_pwrap_regs, staupd_grpen, 0x34); +check_member(mt8183_pwrap_regs, eint_sta0_adr, 0x38); +check_member(mt8183_pwrap_regs, eint_sta1_adr, 0x3C); +check_member(mt8183_pwrap_regs, eint_sta, 0x40); +check_member(mt8183_pwrap_regs, eint_clr, 0x44); +check_member(mt8183_pwrap_regs, eint_ctrl, 0x48); +check_member(mt8183_pwrap_regs, staupd_man_trig, 0x4C); +check_member(mt8183_pwrap_regs, staupd_sta, 0x50); +check_member(mt8183_pwrap_regs, wrap_sta, 0x54); +check_member(mt8183_pwrap_regs, harb_init, 0x58); +check_member(mt8183_pwrap_regs, harb_hprio, 0x5C); +check_member(mt8183_pwrap_regs, hiprio_arb_en, 0x60); +check_member(mt8183_pwrap_regs, harb_sta0, 0x64); +check_member(mt8183_pwrap_regs, harb_sta1, 0x68); +check_member(mt8183_pwrap_regs, harb_sta2, 0x6C); +check_member(mt8183_pwrap_regs, man_en, 0x70); +check_member(mt8183_pwrap_regs, man_cmd, 0x74); +check_member(mt8183_pwrap_regs, man_rdata, 0x78); +check_member(mt8183_pwrap_regs, man_vldclr, 0x7C); +check_member(mt8183_pwrap_regs, wacs0_en, 0x80); +check_member(mt8183_pwrap_regs, init_done0, 0x84); +check_member(mt8183_pwrap_regs, wacs1_en, 0x88); +check_member(mt8183_pwrap_regs, init_done1, 0x8C); +check_member(mt8183_pwrap_regs, wacs2_en, 0x90); +check_member(mt8183_pwrap_regs, init_done2, 0x94); +check_member(mt8183_pwrap_regs, wacs3_en, 0x98); +check_member(mt8183_pwrap_regs, init_done3, 0x9C); +check_member(mt8183_pwrap_regs, wacs_p2p_en, 0xA0); +check_member(mt8183_pwrap_regs, init_done_p2p, 0xA4); +check_member(mt8183_pwrap_regs, wacs_md32_en, 0xA8); +check_member(mt8183_pwrap_regs, init_done_md32, 0xAC); +check_member(mt8183_pwrap_regs, int0_en, 0xB0); +check_member(mt8183_pwrap_regs, int0_flg_raw, 0xB4); +check_member(mt8183_pwrap_regs, int0_flg, 0xB8); +check_member(mt8183_pwrap_regs, int0_clr, 0xBC); +check_member(mt8183_pwrap_regs, int1_en, 0xC0); +check_member(mt8183_pwrap_regs, int1_flg_raw, 0xC4); +check_member(mt8183_pwrap_regs, int1_flg, 0xC8); +check_member(mt8183_pwrap_regs, int1_clr, 0xCC); +check_member(mt8183_pwrap_regs, sig_adr, 0xD0); +check_member(mt8183_pwrap_regs, sig_mode, 0xD4); +check_member(mt8183_pwrap_regs, sig_value, 0xD8); +check_member(mt8183_pwrap_regs, sig_errval, 0xDC); +check_member(mt8183_pwrap_regs, crc_en, 0xE0); +check_member(mt8183_pwrap_regs, timer_en, 0xE4); +check_member(mt8183_pwrap_regs, timer_sta, 0xE8); +check_member(mt8183_pwrap_regs, wdt_unit, 0xEC); +check_member(mt8183_pwrap_regs, wdt_src_en_0, 0xF0); +check_member(mt8183_pwrap_regs, wdt_src_en_1, 0xF4); +check_member(mt8183_pwrap_regs, wdt_flg_0, 0xF8); +check_member(mt8183_pwrap_regs, wdt_flg_1, 0xFC); +check_member(mt8183_pwrap_regs, debug_int_sel, 0x100); +check_member(mt8183_pwrap_regs, dvfs_adr0, 0x104); +check_member(mt8183_pwrap_regs, dvfs_wdata0, 0x108); +check_member(mt8183_pwrap_regs, dvfs_adr1, 0x10C); +check_member(mt8183_pwrap_regs, dvfs_wdata1, 0x110); +check_member(mt8183_pwrap_regs, dvfs_adr2, 0x114); +check_member(mt8183_pwrap_regs, dvfs_wdata2, 0x118); +check_member(mt8183_pwrap_regs, dvfs_adr3, 0x11C); +check_member(mt8183_pwrap_regs, dvfs_wdata3, 0x120); +check_member(mt8183_pwrap_regs, dvfs_adr4, 0x124); +check_member(mt8183_pwrap_regs, dvfs_wdata4, 0x128); +check_member(mt8183_pwrap_regs, dvfs_adr5, 0x12C); +check_member(mt8183_pwrap_regs, dvfs_wdata5, 0x130); +check_member(mt8183_pwrap_regs, dvfs_adr6, 0x134); +check_member(mt8183_pwrap_regs, dvfs_wdata6, 0x138); +check_member(mt8183_pwrap_regs, dvfs_adr7, 0x13C); +check_member(mt8183_pwrap_regs, dvfs_wdata7, 0x140); +check_member(mt8183_pwrap_regs, dvfs_adr8, 0x144); +check_member(mt8183_pwrap_regs, dvfs_wdata8, 0x148); +check_member(mt8183_pwrap_regs, dvfs_adr9, 0x14C); +check_member(mt8183_pwrap_regs, dvfs_wdata9, 0x150); +check_member(mt8183_pwrap_regs, dvfs_adr10, 0x154); +check_member(mt8183_pwrap_regs, dvfs_wdata10, 0x158); +check_member(mt8183_pwrap_regs, dvfs_adr11, 0x15C); +check_member(mt8183_pwrap_regs, dvfs_wdata11, 0x160); +check_member(mt8183_pwrap_regs, dvfs_adr12, 0x164); +check_member(mt8183_pwrap_regs, dvfs_wdata12, 0x168); +check_member(mt8183_pwrap_regs, dvfs_adr13, 0x16C); +check_member(mt8183_pwrap_regs, dvfs_wdata13, 0x170); +check_member(mt8183_pwrap_regs, dvfs_adr14, 0x174); +check_member(mt8183_pwrap_regs, dvfs_wdata14, 0x178); +check_member(mt8183_pwrap_regs, dvfs_adr15, 0x17C); +check_member(mt8183_pwrap_regs, dvfs_wdata15, 0x180); +check_member(mt8183_pwrap_regs, dcxo_enable, 0x184); +check_member(mt8183_pwrap_regs, dcxo_conn_adr0, 0x188); +check_member(mt8183_pwrap_regs, dcxo_conn_wdata0, 0x18C); +check_member(mt8183_pwrap_regs, dcxo_conn_adr1, 0x190); +check_member(mt8183_pwrap_regs, dcxo_conn_wdata1, 0x194); +check_member(mt8183_pwrap_regs, dcxo_nfc_adr0, 0x198); +check_member(mt8183_pwrap_regs, dcxo_nfc_wdata0, 0x19C); +check_member(mt8183_pwrap_regs, dcxo_nfc_adr1, 0x1A0); +check_member(mt8183_pwrap_regs, dcxo_nfc_wdata1, 0x1A4); +check_member(mt8183_pwrap_regs, spminf_sta_0, 0x1A8); +check_member(mt8183_pwrap_regs, spminf_sta_1, 0x1AC); +check_member(mt8183_pwrap_regs, spminf_backup_sta, 0x1B0); +check_member(mt8183_pwrap_regs, scpinf_sta, 0x1B4); +check_member(mt8183_pwrap_regs, cipher_key_sel, 0x1B8); +check_member(mt8183_pwrap_regs, cipher_iv_sel, 0x1BC); +check_member(mt8183_pwrap_regs, cipher_en, 0x1C0); +check_member(mt8183_pwrap_regs, cipher_rdy, 0x1C4); +check_member(mt8183_pwrap_regs, cipher_mode, 0x1C8); +check_member(mt8183_pwrap_regs, cipher_swrst, 0x1CC); +check_member(mt8183_pwrap_regs, dcm_en, 0x1D0); +check_member(mt8183_pwrap_regs, dcm_spi_dbc_prd, 0x1D4); +check_member(mt8183_pwrap_regs, dcm_dbc_prd, 0x1D8); +check_member(mt8183_pwrap_regs, int_gps_auxadc_cmd_addr, 0x1DC); +check_member(mt8183_pwrap_regs, int_gps_auxadc_cmd, 0x1E0); +check_member(mt8183_pwrap_regs, int_gps_auxadc_rdata_addr, 0x1E4); +check_member(mt8183_pwrap_regs, ext_gps_auxadc_rdata_addr, 0x1E8); +check_member(mt8183_pwrap_regs, gpsinf_0_sta, 0x1EC); +check_member(mt8183_pwrap_regs, gpsinf_1_sta, 0x1F0); +check_member(mt8183_pwrap_regs, md_adcinf_ctrl, 0x1F4); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_latest_addr, 0x1F8); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_wp_addr, 0x1FC); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[0], 0x200); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[1], 0x204); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[2], 0x208); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[3], 0x20C); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[4], 0x210); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[5], 0x214); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[6], 0x218); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[7], 0x21C); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[8], 0x220); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[9], 0x224); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[10], 0x228); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[11], 0x22C); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[12], 0x230); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[13], 0x234); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[14], 0x238); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[15], 0x23C); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[16], 0x240); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[17], 0x244); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[18], 0x248); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[19], 0x24C); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[20], 0x250); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[21], 0x254); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[22], 0x258); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[23], 0x25C); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[24], 0x260); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[25], 0x264); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[26], 0x268); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[27], 0x26C); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[28], 0x270); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[29], 0x274); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[30], 0x278); +check_member(mt8183_pwrap_regs, md_auxadc_rdata[31], 0x27C); +check_member(mt8183_pwrap_regs, md_adcinf_0_sta_0, 0x280); +check_member(mt8183_pwrap_regs, md_adcinf_0_sta_1, 0x284); +check_member(mt8183_pwrap_regs, md_adcinf_1_sta_0, 0x288); +check_member(mt8183_pwrap_regs, md_adcinf_1_sta_1, 0x28C); +check_member(mt8183_pwrap_regs, swrst, 0x290); +check_member(mt8183_pwrap_regs, spm_sleep_gating_ctrl, 0x294); +check_member(mt8183_pwrap_regs, scp_sleep_gating_ctrl, 0x298); +check_member(mt8183_pwrap_regs, priority_user_sel_0, 0x29C); +check_member(mt8183_pwrap_regs, priority_user_sel_1, 0x2A0); +check_member(mt8183_pwrap_regs, priority_user_sel_2, 0x2A4); +check_member(mt8183_pwrap_regs, priority_user_sel_3, 0x2A8); +check_member(mt8183_pwrap_regs, priority_user_sel_4, 0x2AC); +check_member(mt8183_pwrap_regs, arbiter_out_sel_0, 0x2B0); +check_member(mt8183_pwrap_regs, arbiter_out_sel_1, 0x2B4); +check_member(mt8183_pwrap_regs, arbiter_out_sel_2, 0x2B8); +check_member(mt8183_pwrap_regs, arbiter_out_sel_3, 0x2BC); +check_member(mt8183_pwrap_regs, arbiter_out_sel_4, 0x2C0); +check_member(mt8183_pwrap_regs, starv_counter_0, 0x2C4); +check_member(mt8183_pwrap_regs, starv_counter_1, 0x2C8); +check_member(mt8183_pwrap_regs, starv_counter_2, 0x2CC); +check_member(mt8183_pwrap_regs, starv_counter_3, 0x2D0); +check_member(mt8183_pwrap_regs, starv_counter_4, 0x2D4); +check_member(mt8183_pwrap_regs, starv_counter_5, 0x2D8); +check_member(mt8183_pwrap_regs, starv_counter_6, 0x2DC); +check_member(mt8183_pwrap_regs, starv_counter_7, 0x2E0); +check_member(mt8183_pwrap_regs, starv_counter_8, 0x2E4); +check_member(mt8183_pwrap_regs, starv_counter_9, 0x2E8); +check_member(mt8183_pwrap_regs, starv_counter_10, 0x2EC); +check_member(mt8183_pwrap_regs, starv_counter_11, 0x2F0); +check_member(mt8183_pwrap_regs, starv_counter_12, 0x2F4); +check_member(mt8183_pwrap_regs, starv_counter_13, 0x2F8); +check_member(mt8183_pwrap_regs, starv_counter_14, 0x2FC); +check_member(mt8183_pwrap_regs, starv_counter_15, 0x300); +check_member(mt8183_pwrap_regs, starv_counter_16, 0x304); +check_member(mt8183_pwrap_regs, starv_counter_0_status, 0x308); +check_member(mt8183_pwrap_regs, starv_counter_1_status, 0x30C); +check_member(mt8183_pwrap_regs, starv_counter_2_status, 0x310); +check_member(mt8183_pwrap_regs, starv_counter_3_status, 0x314); +check_member(mt8183_pwrap_regs, starv_counter_4_status, 0x318); +check_member(mt8183_pwrap_regs, starv_counter_5_status, 0x31C); +check_member(mt8183_pwrap_regs, starv_counter_6_status, 0x320); +check_member(mt8183_pwrap_regs, starv_counter_7_status, 0x324); +check_member(mt8183_pwrap_regs, starv_counter_8_status, 0x328); +check_member(mt8183_pwrap_regs, starv_counter_9_status, 0x32C); +check_member(mt8183_pwrap_regs, starv_counter_10_status, 0x330); +check_member(mt8183_pwrap_regs, starv_counter_11_status, 0x334); +check_member(mt8183_pwrap_regs, starv_counter_12_status, 0x338); +check_member(mt8183_pwrap_regs, starv_counter_13_status, 0x33C); +check_member(mt8183_pwrap_regs, starv_counter_14_status, 0x340); +check_member(mt8183_pwrap_regs, starv_counter_15_status, 0x344); +check_member(mt8183_pwrap_regs, starv_counter_16_status, 0x348); +check_member(mt8183_pwrap_regs, starv_counter_clr, 0x34C); +check_member(mt8183_pwrap_regs, starv_prio_status, 0x350); +check_member(mt8183_pwrap_regs, monitor_ctrl_0, 0x354); +check_member(mt8183_pwrap_regs, monitor_ctrl_1, 0x358); +check_member(mt8183_pwrap_regs, monitor_ctrl_2, 0x35C); +check_member(mt8183_pwrap_regs, monitor_ctrl_3, 0x360); +check_member(mt8183_pwrap_regs, channel_sequence_0, 0x364); +check_member(mt8183_pwrap_regs, channel_sequence_1, 0x368); +check_member(mt8183_pwrap_regs, channel_sequence_2, 0x36C); +check_member(mt8183_pwrap_regs, channel_sequence_3, 0x370); +check_member(mt8183_pwrap_regs, cmd_sequence_0, 0x374); +check_member(mt8183_pwrap_regs, cmd_sequence_1, 0x378); +check_member(mt8183_pwrap_regs, cmd_sequence_2, 0x37C); +check_member(mt8183_pwrap_regs, cmd_sequence_3, 0x380); +check_member(mt8183_pwrap_regs, cmd_sequence_4, 0x384); +check_member(mt8183_pwrap_regs, cmd_sequence_5, 0x388); +check_member(mt8183_pwrap_regs, cmd_sequence_6, 0x38C); +check_member(mt8183_pwrap_regs, cmd_sequence_7, 0x390); +check_member(mt8183_pwrap_regs, wdata_sequence_0, 0x394); +check_member(mt8183_pwrap_regs, wdata_sequence_1, 0x398); +check_member(mt8183_pwrap_regs, wdata_sequence_2, 0x39C); +check_member(mt8183_pwrap_regs, wdata_sequence_3, 0x3A0); +check_member(mt8183_pwrap_regs, wdata_sequence_4, 0x3A4); +check_member(mt8183_pwrap_regs, wdata_sequence_5, 0x3A8); +check_member(mt8183_pwrap_regs, wdata_sequence_6, 0x3AC); +check_member(mt8183_pwrap_regs, wdata_sequence_7, 0x3B0); +check_member(mt8183_pwrap_regs, debug_sw_driver_0, 0x3B4); +check_member(mt8183_pwrap_regs, debug_sw_driver_1, 0x3B8); +check_member(mt8183_pwrap_regs, debug_sw_driver_2, 0x3BC); +check_member(mt8183_pwrap_regs, debug_sw_driver_3, 0x3C0); +check_member(mt8183_pwrap_regs, debug_sw_driver_4, 0x3C4); +check_member(mt8183_pwrap_regs, debug_sw_driver_5, 0x3C8); +check_member(mt8183_pwrap_regs, bwc_options, 0x3CC); +check_member(mt8183_pwrap_regs, reserved1, 0x3D0); +check_member(mt8183_pwrap_regs, wacs0_cmd, 0xC00); +check_member(mt8183_pwrap_regs, wacs0_rdata, 0xC04); +check_member(mt8183_pwrap_regs, wacs0_vldclr, 0xC08); +check_member(mt8183_pwrap_regs, reserved2, 0xC0C); +check_member(mt8183_pwrap_regs, wacs1_cmd, 0xC10); +check_member(mt8183_pwrap_regs, wacs1_rdata, 0xC14); +check_member(mt8183_pwrap_regs, wacs1_vldclr, 0xC18); +check_member(mt8183_pwrap_regs, reserved3, 0xC1C); +check_member(mt8183_pwrap_regs, wacs2_cmd, 0xC20); +check_member(mt8183_pwrap_regs, wacs2_rdata, 0xC24); +check_member(mt8183_pwrap_regs, wacs2_vldclr, 0xC28); +check_member(mt8183_pwrap_regs, reserved4, 0xC2C); +check_member(mt8183_pwrap_regs, wacs3_cmd, 0xC30); +check_member(mt8183_pwrap_regs, wacs3_rdata, 0xC34); +check_member(mt8183_pwrap_regs, wacs3_vldclr, 0xC38); + +static struct mt8183_pwrap_regs * const mtk_pwrap = (void *)PWRAP_BASE; + +enum { + WACS2 = 1 << 2 +}; + +/* PMIC registers */ +enum { + PMIC_BASE = 0x0000, + PMIC_SMT_CON1 = PMIC_BASE + 0x0030, + PMIC_DRV_CON1 = PMIC_BASE + 0x0038, + PMIC_FILTER_CON0 = PMIC_BASE + 0x0040, + PMIC_GPIO_PULLEN0_CLR = PMIC_BASE + 0x0098, + PMIC_RG_SPI_CON0 = PMIC_BASE + 0x0408, + PMIC_RG_SPI_RECORD0 = PMIC_BASE + 0x040A, + PMIC_DEW_DIO_EN = PMIC_BASE + 0x040C, + PMIC_DEW_READ_TEST = PMIC_BASE + 0x040E, + PMIC_DEW_WRITE_TEST = PMIC_BASE + 0x0410, + PMIC_DEW_CRC_EN = PMIC_BASE + 0x0414, + PMIC_DEW_CRC_VAL = PMIC_BASE + 0x0416, + PMIC_DEW_RDDMY_NO = PMIC_BASE + 0x0426, + PMIC_CPU_INT_STA = PMIC_BASE + 0x042E, + PMIC_RG_SPI_CON2 = PMIC_BASE + 0x0432, + PMIC_RG_SPI_CON3 = PMIC_BASE + 0x0434, + PMIC_RG_SPI_CON4 = PMIC_BASE + 0x0436, + PMIC_RG_SPI_CON5 = PMIC_BASE + 0x0438, + PMIC_RG_SPI_CON6 = PMIC_BASE + 0x043A, + PMIC_RG_SPI_CON7 = PMIC_BASE + 0x043C, + PMIC_RG_SPI_CON8 = PMIC_BASE + 0x043E, + PMIC_RG_SPI_CON13 = PMIC_BASE + 0x0448, + PMIC_SPISLV_KEY = PMIC_BASE + 0x044A, + PMIC_PPCCTL0 = PMIC_BASE + 0x0A08, + PMIC_AUXADC_ADC17 = PMIC_BASE + 0x10AA, + PMIC_AUXADC_ADC31 = PMIC_BASE + 0x10C6, + PMIC_AUXADC_ADC32 = PMIC_BASE + 0x10C8, + PMIC_AUXADC_ADC35 = PMIC_BASE + 0x10CE, + PMIC_AUXADC_RQST0 = PMIC_BASE + 0x1108, + PMIC_AUXADC_RQST1 = PMIC_BASE + 0x110A, +}; + +enum { + E_CLK_EDGE = 1, + E_CLK_LAST_SETTING +}; + +enum pmic_regck { + REG_CLOCK_18MHZ = 1, + REG_CLOCK_SAFE_MODE +}; + +enum { + GPS_MAIN = 0x40, + GPS_SUBSYS = 0x80 +}; +#endif /* __SOC_MEDIATEK_MT8183_PMIC_WRAP_H__ */ diff --git a/src/soc/mediatek/mt8183/pmic_wrap.c b/src/soc/mediatek/mt8183/pmic_wrap.c new file mode 100644 index 0000000..bad979a --- /dev/null +++ b/src/soc/mediatek/mt8183/pmic_wrap.c @@ -0,0 +1,311 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <soc/infracfg.h> +#include <soc/pll.h> +#include <soc/pmic_wrap.h> + +static void pwrap_soft_reset(void) +{ + write32(&mt8183_infracfg->infra_globalcon_rst2_set, 0x1); + write32(&mt8183_infracfg->infra_globalcon_rst2_clr, 0x1); +} + +static void pwrap_spi_clk_set(void) +{ + write32(&mtk_topckgen->clk_cfg_5_clr, 0x93000000); + write32(&mtk_topckgen->clk_cfg_5_set, 0x1 << 24); + write32(&mtk_topckgen->clk_cfg_update, 0x1 << 23); + + write32(&mt8183_infracfg->module_sw_cg_0_set, 0x0000000F); + write32(&mt8183_infracfg->module_sw_cg_2_set, 0x00000100); + + pwrap_soft_reset(); + + write32(&mt8183_infracfg->module_sw_cg_0_clr, 0x0000000F); + write32(&mt8183_infracfg->module_sw_cg_2_clr, 0x00000100); +} + +static s32 pwrap_init_dio(u16 dio_en) +{ + u32 rdata = 0x0; + + pwrap_write_nochk(PMIC_DEW_DIO_EN, dio_en); + do { + rdata = read32(&mtk_pwrap->wacs2_rdata); + } while (wait_for_idle_and_sync(rdata)); + + write32(&mtk_pwrap->dio_en, dio_en); + return 0; +} + +static void pwrap_lock_spislvreg(void) +{ + pwrap_write_nochk(PMIC_SPISLV_KEY, 0x0); +} + +static void pwrap_initstaupd(void) +{ + write32(&mtk_pwrap->staupd_grpen, 0xf5); + + /* CRC */ + pwrap_write_nochk(PMIC_DEW_CRC_EN, 0x1); + write32(&mtk_pwrap->crc_en, 0x1); + write32(&mtk_pwrap->sig_adr, PMIC_DEW_CRC_VAL); + + write32(&mtk_pwrap->eint_sta0_adr, PMIC_CPU_INT_STA); + + /* MD ADC Interface */ + write32(&mtk_pwrap->md_auxadc_rdata_latest_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + write32(&mtk_pwrap->md_auxadc_rdata_wp_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + for (size_t i = 0; i < 32; i++) + write32(&mtk_pwrap->md_auxadc_rdata[i], + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + + write32(&mtk_pwrap->int_gps_auxadc_cmd_addr, + (PMIC_AUXADC_RQST1 << 16) + PMIC_AUXADC_RQST0); + write32(&mtk_pwrap->int_gps_auxadc_cmd, (GPS_MAIN << 16) + GPS_SUBSYS); + write32(&mtk_pwrap->int_gps_auxadc_rdata_addr, + (PMIC_AUXADC_ADC32 << 16) + PMIC_AUXADC_ADC17); + + write32(&mtk_pwrap->ext_gps_auxadc_rdata_addr, PMIC_AUXADC_ADC31); +} + +static void pwrap_starve_set(void) +{ + write32(&mtk_pwrap->harb_hprio, 0xf); + write32(&mtk_pwrap->starv_counter_0, 0x402); + write32(&mtk_pwrap->starv_counter_1, 0x403); + write32(&mtk_pwrap->starv_counter_2, 0x403); + write32(&mtk_pwrap->starv_counter_3, 0x403); + write32(&mtk_pwrap->starv_counter_4, 0x40f); + write32(&mtk_pwrap->starv_counter_5, 0x420); + write32(&mtk_pwrap->starv_counter_6, 0x428); + write32(&mtk_pwrap->starv_counter_7, 0x428); + write32(&mtk_pwrap->starv_counter_8, 0x413); + write32(&mtk_pwrap->starv_counter_9, 0x417); + write32(&mtk_pwrap->starv_counter_10, 0x417); + write32(&mtk_pwrap->starv_counter_11, 0x47c); + write32(&mtk_pwrap->starv_counter_12, 0x47c); + write32(&mtk_pwrap->starv_counter_13, 0x740); + write32(&mtk_pwrap->starv_counter_16, 0x740); +} + +static void pwrap_enable(void) +{ + write32(&mtk_pwrap->hiprio_arb_en, 0x3fa75); + write32(&mtk_pwrap->wacs0_en, 0x1); + write32(&mtk_pwrap->wacs2_en, 0x1); + write32(&mtk_pwrap->wacs_p2p_en, 0x1); + write32(&mtk_pwrap->wacs_md32_en, 0x1); + write32(&mtk_pwrap->staupd_ctrl, 0x5); + write32(&mtk_pwrap->wdt_unit, 0xf); + write32(&mtk_pwrap->wdt_src_en_0, 0xffffffff); + write32(&mtk_pwrap->wdt_src_en_1, 0xffffffff); + write32(&mtk_pwrap->timer_en, 0x1); + write32(&mtk_pwrap->int0_en, 0xffffffff); + write32(&mtk_pwrap->int1_en, 0xeef7ffff); +} + +static s32 pwrap_init_sistrobe(void) +{ + u16 rdata; + int si_sample_ctrl; + int test_data[30] = { + 0x6996, 0x9669, 0x6996, 0x9669, 0x6996, 0x9669, 0x6996, + 0x9669, 0x6996, 0x9669, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, + 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x1B27, + 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, + 0x1B27, 0x1B27}; + + for (si_sample_ctrl = 0; si_sample_ctrl < 16; si_sample_ctrl++) { + write32(&mtk_pwrap->si_sample_ctrl, si_sample_ctrl << 5); + + pwrap_read_nochk(PMIC_DEW_READ_TEST, &rdata); + if (rdata == DEFAULT_VALUE_READ_TEST) + break; + } + + if (si_sample_ctrl == 16) + return E_CLK_EDGE; + + if (si_sample_ctrl == 15) + return E_CLK_LAST_SETTING; + + for (int si_dly = 0; si_dly < 10; si_dly++) { + pwrap_write_nochk(PMIC_RG_SPI_CON2, si_dly); + + int error = 0; + for (size_t i = 0; i < 30; i++) { + pwrap_write_nochk(PMIC_DEW_WRITE_TEST, test_data[i]); + pwrap_read_nochk(PMIC_DEW_WRITE_TEST, &rdata); + if ((rdata & 0x7fff) != (test_data[i] & 0x7fff)) { + /* Data boundary is found */ + error = 1; + break; + } + } + if (error == 1) + break; + } + + /* Change The Sampling Clock Edge To The Next One. */ + write32(&mtk_pwrap->si_sample_ctrl, ++si_sample_ctrl << 5); + + /* Read Test */ + pwrap_read_nochk(PMIC_DEW_READ_TEST, &rdata); + if (rdata != DEFAULT_VALUE_READ_TEST) { + pwrap_err("rdata = %x, exp = 0x5aa5\n", rdata); + return 0x10; + } + + return 0; +} + +static void pwrap_init_spislv(void) +{ + /* Turn on IO filter function */ + pwrap_write_nochk(PMIC_FILTER_CON0, 0xf0); + /* Turn on IO SMT function to improve noise immunity */ + pwrap_write_nochk(PMIC_SMT_CON1, 0xf); + /* Turn off IO pull function for power saving */ + pwrap_write_nochk(PMIC_GPIO_PULLEN0_CLR, 0xf0); + /* Turn off IO pull function for power saving */ + pwrap_write_nochk(PMIC_RG_SPI_CON0, 0x1); + /* Set PMIC GPIO driving current to 4mA */ + pwrap_write_nochk(PMIC_DRV_CON1, 0x8888); +} + +static void pwrap_init_reg_clock(u16 regck_sel) +{ + write32(&mtk_pwrap->ext_ck_write, 0x1); + + pwrap_write_nochk(PMIC_DEW_RDDMY_NO, 0x8); + write32(&mtk_pwrap->rddmy, 0x8); + + /* Config SPI Waveform according to reg clk */ + uint32_t value = (regck_sel == REG_CLOCK_18MHZ) ? 0 : 0x0f0f; + write32(&mtk_pwrap->cshext_write, value); + write32(&mtk_pwrap->cshext_read, value); + write32(&mtk_pwrap->cslext_write, value); + write32(&mtk_pwrap->cslext_read, value); +} + +s32 pwrap_init(void) +{ + s32 sub_return = 0, sub_return1 = 0; + u16 rdata; + + pwrap_spi_clk_set(); + + /* Reset spislv */ + sub_return = pwrap_reset_spislv(); + if (sub_return != 0) { + pwrap_err("reset_spislv fail, ret=%x\n", sub_return); + return E_PWR_INIT_RESET_SPI; + } + + /* Enable WRAP */ + write32(&mtk_pwrap->wrap_en, 0x1); + + /* Enable WACS2 */ + write32(&mtk_pwrap->wacs2_en, 0x1); + write32(&mtk_pwrap->hiprio_arb_en, WACS2); /* ONLY WACS2 */ + + /* SPI Waveform Configuration. 0:safe mode, 1:18MHz */ + pwrap_init_reg_clock(REG_CLOCK_18MHZ); + + /* SPI Slave Configuration */ + pwrap_init_spislv(); + + /* Enable DIO mode */ + sub_return = pwrap_init_dio(1); + if (sub_return != 0) { + pwrap_err("dio test error, err=%x, ret=%x\n", 0x11, sub_return); + return E_PWR_INIT_DIO; + } + + /* Input data calibration flow; */ + sub_return = pwrap_init_sistrobe(); + if (sub_return != 0) { + pwrap_err("InitSiStrobe fail,ret=%x\n", sub_return); + return E_PWR_INIT_SIDLY; + } + + /* + * Write test using WACS2, + * make sure the read/write function ready. + */ + sub_return = pwrap_write_nochk(PMIC_DEW_WRITE_TEST, WRITE_TEST_VALUE); + sub_return1 = pwrap_read_nochk(PMIC_DEW_WRITE_TEST, &rdata); + if (rdata != WRITE_TEST_VALUE || sub_return || sub_return1) { + pwrap_err("write error, rdata=%#x, return=%#x, return1=%#x\n", + rdata, sub_return, sub_return1); + return E_PWR_INIT_WRITE_TEST; + } + + /* + * Status update function initialization + * 1. Signature Checking using CRC (CRC 0 only) + * 2. EINT update + * 3. Read back Auxadc thermal data for GPS + */ + pwrap_initstaupd(); + + write32(&mtk_pwrap->priority_user_sel_2, 0x0b09080a); + write32(&mtk_pwrap->arbiter_out_sel_2, 0x0b080a09); + + pwrap_starve_set(); + + pwrap_enable(); + + /* Initialization Done */ + write32(&mtk_pwrap->init_done0, 0x1); + write32(&mtk_pwrap->init_done2, 0x1); + write32(&mtk_pwrap->init_done_p2p, 0x1); + write32(&mtk_pwrap->init_done_md32, 0x1); + + /* Lock SPISLV Registers */ + pwrap_lock_spislvreg(); + + /* Enable Command Recording */ + sub_return = pwrap_write_nochk(PMIC_RG_SPI_RECORD0, 0x1); + if (sub_return != 0) + pwrap_err("enable spi debug fail, ret=%x\n", sub_return); + + /* Clear Last three command */ + sub_return = pwrap_write_nochk(PMIC_RG_SPI_CON13, 0x1); + if (sub_return != 0) + pwrap_err("clear record command fail, ret=%x\n", sub_return); + sub_return = pwrap_write_nochk(PMIC_RG_SPI_CON13, 0x0); + if (sub_return != 0) + pwrap_err("clear record command fail, ret=%x\n", sub_return); + + /* Disable monitor MD HW channel (CH8) */ + write32(&mtk_pwrap->monitor_ctrl_1, 0x1feff); + /* Record all addr (mask+addr) */ + write32(&mtk_pwrap->monitor_ctrl_2, 0x0); + /* Record all wdata (mask+addr) */ + write32(&mtk_pwrap->monitor_ctrl_3, 0x0); + /* Clear log */ + write32(&mtk_pwrap->monitor_ctrl_0, 0x8); + /* Reenable */ + write32(&mtk_pwrap->monitor_ctrl_0, 0x1); + + return 0; +}
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Tristan Hsieh (Code Review)