Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34786 )
Change subject: mb/toshiba: Add A300-1ME ......................................................................
mb/toshiba: Add A300-1ME
Mainboard real name (to find schematics) is Inventec Potomac 10G. Vendor firmware is InsydeH20 EFI Rev. 3.5 and shows postcodes on LPC.
This thing is a PM45/ICH9M notebook with a WPCE775 EC. It usually boots from LPC via EC, but also has space for another flash chip, directly attached to SPI.
Working: - usbdebug with FT2232H (left side, the non-eSATA USB port) - postcodes via LPC (debug card on WLAN card slot) with vendor firmware coreboot may not be printing any postcodes on this platform, so this may explain why postcodes don't show with coreboot. But the hw works. - running coreboot off the ICH SPI flash chip - fan runs at a high speed by default (no risk of overheating)
Not working: - raminit: dies with: "DDR2 not supported at this time." - some watchdog trips after a few seconds (likely EC watchdog) (though coreboot currently dies first)
Change-Id: Ifcdfadd2506962bc797b174b4d656e9201f7a40d Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/toshiba/Kconfig A src/mainboard/toshiba/Kconfig.name A src/mainboard/toshiba/a300-1me/Kconfig A src/mainboard/toshiba/a300-1me/Kconfig.name A src/mainboard/toshiba/a300-1me/Makefile.inc A src/mainboard/toshiba/a300-1me/acpi/battery.asl A src/mainboard/toshiba/a300-1me/acpi/ec.asl A src/mainboard/toshiba/a300-1me/acpi/ec2.asl A src/mainboard/toshiba/a300-1me/acpi/gpe.asl A src/mainboard/toshiba/a300-1me/acpi/ich9_pci_irqs.asl A src/mainboard/toshiba/a300-1me/acpi/mainboard.asl A src/mainboard/toshiba/a300-1me/acpi/platform.asl A src/mainboard/toshiba/a300-1me/acpi/superio.asl A src/mainboard/toshiba/a300-1me/acpi/thermal.asl A src/mainboard/toshiba/a300-1me/acpi_tables.c A src/mainboard/toshiba/a300-1me/blc.c A src/mainboard/toshiba/a300-1me/board_info.txt A src/mainboard/toshiba/a300-1me/cmos.layout A src/mainboard/toshiba/a300-1me/cstates.c A src/mainboard/toshiba/a300-1me/devicetree.cb A src/mainboard/toshiba/a300-1me/dsdt.asl A src/mainboard/toshiba/a300-1me/fadt.c A src/mainboard/toshiba/a300-1me/gpio.c A src/mainboard/toshiba/a300-1me/hda_verb.c A src/mainboard/toshiba/a300-1me/mainboard.c A src/mainboard/toshiba/a300-1me/romstage.c A src/mainboard/toshiba/a300-1me/smistuff.c 27 files changed, 1,899 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/34786/1
diff --git a/src/mainboard/toshiba/Kconfig b/src/mainboard/toshiba/Kconfig new file mode 100644 index 0000000..609b15d --- /dev/null +++ b/src/mainboard/toshiba/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_TOSHIBA + +choice + prompt "Mainboard model" + +source "src/mainboard/toshiba/*/Kconfig.name" + +endchoice + +source "src/mainboard/toshiba/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "TOSHIBA" + +endif # VENDOR_TOSHIBA diff --git a/src/mainboard/toshiba/Kconfig.name b/src/mainboard/toshiba/Kconfig.name new file mode 100644 index 0000000..47dbb59 --- /dev/null +++ b/src/mainboard/toshiba/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_TOSHIBA + bool "TOSHIBA" diff --git a/src/mainboard/toshiba/a300-1me/Kconfig b/src/mainboard/toshiba/a300-1me/Kconfig new file mode 100644 index 0000000..8099b7b --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/Kconfig @@ -0,0 +1,33 @@ +if BOARD_TOSHIBA_A300_1ME + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYSTEM_TYPE_LAPTOP + select CPU_INTEL_SOCKET_BGA956 + select NORTHBRIDGE_INTEL_GM45 + select SOUTHBRIDGE_INTEL_I82801IX + select BOARD_ROMSIZE_KB_2048 # FIXME: that's the size of my flash chip + #select DRIVERS_GENERIC_IOAPIC + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select EC_ACPI + select HAVE_OPTION_TABLE + select INTEL_INT15 + +config MAINBOARD_DIR + string + default toshiba/a300-1me + +config MAINBOARD_PART_NUMBER + string + default "A300-1ME" + +config MAX_CPUS + int + default 2 + +config CBFS_SIZE + hex + default ROM_SIZE + +endif # BOARD_TOSHIBA_A300_1ME diff --git a/src/mainboard/toshiba/a300-1me/Kconfig.name b/src/mainboard/toshiba/a300-1me/Kconfig.name new file mode 100644 index 0000000..8bc568d --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_TOSHIBA_A300_1ME + bool "A300-1ME" diff --git a/src/mainboard/toshiba/a300-1me/Makefile.inc b/src/mainboard/toshiba/a300-1me/Makefile.inc new file mode 100644 index 0000000..21bbe39 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/Makefile.inc @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 secunet Security Networks AG +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y = gpio.c + +ramstage-y += cstates.c +ramstage-y += blc.c diff --git a/src/mainboard/toshiba/a300-1me/acpi/battery.asl b/src/mainboard/toshiba/a300-1me/acpi/battery.asl new file mode 100644 index 0000000..2f793d8 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/acpi/battery.asl @@ -0,0 +1,226 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Name(\CBA1, 0x60) +Name(\CBA2, 0x60) + +/* ACPI doesn't care if capacity is given in mWh or mAh, + but it has to be consistent */ + +Device (BAT1) +{ + Name(_HID, EisaId("PNP0C0A")) + Name(_UID, 1) + + Name(_PCL, Package(){ _SB }) + Name(PSTA, 0x1f) + + /* battery information */ + Name(PBIF, Package() { + 0x01, // power unit + 0x01, // design capacity (mWh/mAh), updated by UPBI + 0x01, // last full charge capacity (mWh/mAh), updated by UPBI + 0x01, // battery technology: "rechargeable" + 0x01, // design voltage (mV), updated by UPBI + 0x0294, // design capacity of warning (mWh/mAh) + 0x014a, // design capacity of low (mWh/mAh) + 0x42, // battery capacity granularity between low and warning + 0x42, // battery capacity granularity between warning and full + "BAT1", // Name + "001 ", // Number + "LION", // Type + "JSE" // Vendor + }) + /* battery status */ + /* dummy values, filled in by UPBS */ + Name(PBST, Package() { + 0x00, // battery state + // bit0: discharging + // bit1: charging + // bit2: critical energy state + 0x01, // battery present rate (mW/mA) + 0x01, // remaining capacity (mW/mA) + 0x01 // battery present voltage (mV) + }) + + /* Status */ + Method(_STA, 0) + { + If(_SB.PCI0.LPCB.EC0.ECON) { + If(_SB.PCI0.LPCB.EC0.B1PR) { + If(_SB.PCI0.LPCB.EC0.B1CH) { + Return(0x1f) + } + } + } + Return(0x0f) + } + + /* Battery Info */ + Method(_BIF, 0) + { + If(_SB.PCI0.LPCB.EC0.ECON) { + Store (_SB.PCI0.LPCB.EC0.B1DW, Index(PBIF, 1)) + Store (_SB.PCI0.LPCB.EC0.B1FW, Index(PBIF, 2)) + Store (_SB.PCI0.LPCB.EC0.B1DV, Index(PBIF, 4)) + } + + Return(PBIF) + } + + /* Battery Status */ + Method(_BST, 0) + { + If(_SB.PCI0.LPCB.EC0.ECON) { + Store (_SB.PCI0.LPCB.EC0.B1PW, Local0) + If (LGreaterEqual (Local0, 0x8000)) { + Subtract (0x10000, Local0, Local0) + } + Store (Local0, Index(PBST, 1)) + Store (_SB.PCI0.LPCB.EC0.B1PV, Index(PBST, 3)) + + Store (_SB.PCI0.LPCB.EC0.B1RW, Index(PBST, 2)) + + If (_SB.PCI0.LPCB.EC0.ACCH) { + If (_SB.PCI0.LPCB.EC0.B1CH) { + If (_SB.PCI0.LPCB.EC0.B1CG) { + Store (2, Index(PBST, 0)) + } + } + } Else { + If (_SB.PCI0.LPCB.EC0.B1LO) { + Store (5, Index(PBST, 0)) + } Else { + Store (1, Index(PBST, 0)) + } + } + } + + Return(PBST) + } + +} + +Device (BAT2) +{ + Name(_HID, EisaId("PNP0C0A")) + Name(_UID, 2) + + Name(_PCL, Package(){ _SB }) + Name(PSTA, 0x1f) + + /* battery information */ + Name(PBIF, Package() { + 0x01, // power unit + 0x01, // design capacity (mWh/mAh), updated by UPBI + 0x01, // last full charge capacity (mWh/mAh), updated by UPBI + 0x01, // battery technology: "rechargeable" + 0x01, // design voltage (mV), updated by UPBI + 0x0294, // design capacity of warning (mWh/mAh) + 0x014a, // design capacity of low (mWh/mAh) + 0x42, // battery capacity granularity between low and warning + 0x42, // battery capacity granularity between warning and full + "BAT1", // Name + "002 ", // Number + "LION", // Type + "JSE" // Vendor + }) + /* battery status */ + /* dummy values, filled in by UPBS */ + Name(PBST, Package() { + 0x00, // battery state + // bit0: discharging + // bit1: charging + // bit2: critical energy state + 0x01, // battery present rate (mW/mA) + 0x01, // remaining capacity (mW/mA) + 0x01 // battery present voltage (mV) + }) + + /* Status */ + Method(_STA, 0) + { + If(_SB.PCI0.LPCB.EC0.ECON) { + If(_SB.PCI0.LPCB.EC0.B2PR) { + If(_SB.PCI0.LPCB.EC0.B2CH) { + Return(0x1f) + } + } + } + Return(0x0f) + } + + /* Battery Info */ + Method(_BIF, 0) + { + If(_SB.PCI0.LPCB.EC0.ECON) { + Store (_SB.PCI0.LPCB.EC0.B2DW, Index(PBIF, 1)) + Store (_SB.PCI0.LPCB.EC0.B2FW, Index(PBIF, 2)) + Store (_SB.PCI0.LPCB.EC0.B2DV, Index(PBIF, 4)) + } + + Return(PBIF) + } + + /* Battery Status */ + Method(_BST, 0) + { + If(_SB.PCI0.LPCB.EC0.ECON) { + Store (_SB.PCI0.LPCB.EC0.B2PW, Local0) + If (LGreaterEqual (Local0, 0x8000)) { + Subtract (0x10000, Local0, Local0) + } + Store (Local0, Index(PBST, 1)) + Store (_SB.PCI0.LPCB.EC0.B2PV, Index(PBST, 3)) + + Store (_SB.PCI0.LPCB.EC0.B2RW, Index(PBST, 2)) + + If (_SB.PCI0.LPCB.EC0.ACCH) { + If (_SB.PCI0.LPCB.EC0.B2CH) { + If (_SB.PCI0.LPCB.EC0.B2CG) { + Store (2, Index(PBST, 0)) + } + } + } Else { + If (_SB.PCI0.LPCB.EC0.B2LO) { + Store (5, Index(PBST, 0)) + } Else { + Store (1, Index(PBST, 0)) + } + } + } + + Return(PBST) + } + +} + +Device (ADP1) +{ + Name (_HID, "ACPI0003") + Method (_PSR, 0) + { + Store (_SB.PCI0.LPCB.EC0.ACCH, PWRS) + Stall (0x02) + Return (PWRS) + } + + Method (_PCL, 0) + { + Return (_SB) + } +} diff --git a/src/mainboard/toshiba/a300-1me/acpi/ec.asl b/src/mainboard/toshiba/a300-1me/acpi/ec.asl new file mode 100644 index 0000000..48630b0 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/acpi/ec.asl @@ -0,0 +1 @@ +// dummy diff --git a/src/mainboard/toshiba/a300-1me/acpi/ec2.asl b/src/mainboard/toshiba/a300-1me/acpi/ec2.asl new file mode 100644 index 0000000..aef4d32 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/acpi/ec2.asl @@ -0,0 +1,192 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC0) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 1) + + Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI + Name (ECON, 0) + Name (QEVT, 0) + + OperationRegion(ERAM, EmbeddedControl, 0x00, 0xff) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset(0xb1), + CPWR, 1, + ACCH, 1, // AC connected (charger present) + B1PR, 1, // battery 1 present + B2PR, 1, // battery 2 present + B1CH, 1, // battery 1 charged + B2CH, 1, // battery 2 charged + Offset(0xb2), + B1CG, 1, // battery 1 charging + B2CG, 1, // battery 2 charging + B1LO, 1, // battery 1 low + B2LO, 1, // battery 2 low + Offset(0xb3), + B1DW, 16, // battery 1 design capacity + B1FW, 16, // battery 1 last full charge capacity + B1DV, 16, // battery 1 design voltage + B1PW, 16, // battery 1 present capacity + Offset(0xbd), + B1PV, 16, // battery 1 present voltage + Offset(0xc1), + B2DW, 16, // battery 2 design capacity + B2FW, 16, // battery 2 last full charge capacity + B2DV, 16, // battery 2 design voltage + B2PW, 16, // battery 2 present capacity + Offset(0xcb), + B2PV, 16, // battery 2 present voltage + Offset(0xcf), + FDDI, 1, // floppy on lpt indicator? + LIDC, 1, // LID switch + Offset(0xd0), + TCPU, 8, // T_CPU in deg Celcius + Offset(0xd6), + /* exact purpose of these three is guessed, + but it's something about cooling */ + ALRL, 1, // active cooling low limit + ALRH, 1, // active cooling high limit + ALRC, 1, // active cooling clear + Offset(0xe8), + B1RW, 16, // battery 1 remaining capacity + B2RW, 16, // battery 2 remaining capacity + } + + Method (_CRS, 0) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 1, 1) + IO (Decode16, 0x66, 0x66, 1, 1) + }) + + Return (ECMD) + } + + Method (_REG, 2) + { + // This method is needed by Windows XP/2000 for + // EC initialization before a driver is loaded + + If (LEqual(Arg0, 0x03)) { + Store (Arg1, ECON) + } + } + + // EC Query methods + + Method (_Q11, 0) + { + Store("_Q11: Fn-F8 (Sleep Button) pressed", Debug) + Notify(SLPB, 0x80) + } + + Method (_Q30, 0) + { + Store("_Q30: AC In", Debug) + Notify(ADP1, 0x80) // Tell the Power Adapter + PNOT() // and the CPU and Battery + } + + Method (_Q31, 0) + { + Store("_Q31: AC Out", Debug) + Notify(ADP1, 0x80) // Tell the Power Adapter + PNOT() // and the CPU and Battery + } + + Method (_Q32, 0) + { + Store("_Q32: Bat1 In", Debug) + Notify(BAT1, 0x81) + } + + Method (_Q33, 0) + { + Store("_Q33: Bat1 Out", Debug) + Notify(BAT1, 0x81) + } + + Method (_Q34, 0) + { + Store("_Q34: Bat2 In", Debug) + Notify(BAT2, 0x81) + } + + Method (_Q35, 0) + { + Store("_Q35: Bat2 Out", Debug) + Notify(BAT2, 0x81) + } + + Method (_Q36, 0) + { + Store("_Q36: Bat1 Low Power", Debug) + Notify(BAT1, 0x80) + } + + Method (_Q37, 0) + { + Store("_Q37: Bat1 Full Charge", Debug) + Notify(BAT1, 0x80) + } + + Method (_Q38, 0) + { + Store("_Q38: Bat2 Low Power", Debug) + Notify(BAT2, 0x80) + } + + Method (_Q39, 0) + { + Store("_Q39: Bat2 Full Charge", Debug) + Notify(BAT2, 0x80) + } + + Method (_Q40, 0) + { + Store("_Q40: LID Open/Close", Debug) + Notify(LID0, 0x80) + } + + Method (_Q41, 0) + { + Store("_Q41: Floppy on Parallel Port: Call the Museum!", Debug) + } + + Method (_Q50, 0) + { + Store("_Q50: Processor is hot", Debug) + Notify(_TZ.THRM, 0x80) + } + + Method (_Q51, 0) + { + Store("_Q51: Processor is boiling", Debug) + Notify(_TZ.THRM, 0x80) + } + + Method (_Q52, 0) + { + Store("_Q52: Processor is burning", Debug) + Notify(_TZ.THRM, 0x80) + } + +} diff --git a/src/mainboard/toshiba/a300-1me/acpi/gpe.asl b/src/mainboard/toshiba/a300-1me/acpi/gpe.asl new file mode 100644 index 0000000..5ba3538 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/acpi/gpe.asl @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (_GPE) +{ + /* The event numbers correspond to the bit numbers in the + * GPE0_EN register PMBASE + 0x28. + */ + /* IMO we don't need empty Methods here. If we don't specify + one and don't set the GPE0_EN bit Linux won't neither enable + it. - Nico */ + + // Thermal Event - original BIOS doesn't have it + Method (_L00, 0) + { + /* FIXME: We should enable throttling here. */ + } + + // Hot Plug + Method (_L01, 0) + { + + } + + // USB1 + Method (_L03, 0) + { + + } + + // USB2 + Method (_L04, 0) + { + + } + + // USB5 + Method (_L05, 0) + { + + } + + // _L06 TCOSCI + + // SMBus Wake Status + Method (_L07, 0) + { + + } + + // COM1/COM2 (RI) + Method (_L08, 0) + { + + } + + // PCIe + Method (_L09, 0) + { + + } + + // _L0A BatLow / Quick Resume + + // PME + Method (_L0B, 0) + { + + } + + // USB3 + Method (_L0C, 0) + { + + } + + // PME B0 + Method (_L0D, 0) + { + + } + + // USB4 + Method (_L0E, 0) + { + + } + + // _L10 - _L1f: GPIn + + // GPI8 + Method (_L18, 0) + { + + } + + // USB6 + Method (_L20, 0) + { + + } +} diff --git a/src/mainboard/toshiba/a300-1me/acpi/ich9_pci_irqs.asl b/src/mainboard/toshiba/a300-1me/acpi/ich9_pci_irqs.asl new file mode 100644 index 0000000..b206c2b --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/acpi/ich9_pci_irqs.asl @@ -0,0 +1,104 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH9 + */ + +/* TODO: which slots are actually relevant? */ +If (PICM) { + Return (Package() { + // PCI Slot 1 routes ABCD + Package() { 0x0000ffff, 0, 0, 16}, + Package() { 0x0000ffff, 1, 0, 17}, + Package() { 0x0000ffff, 2, 0, 18}, + Package() { 0x0000ffff, 3, 0, 19}, + + // PCI Slot 2 routes BCDA + Package() { 0x0001ffff, 0, 0, 17}, + Package() { 0x0001ffff, 1, 0, 18}, + Package() { 0x0001ffff, 2, 0, 19}, + Package() { 0x0001ffff, 3, 0, 16}, + + // PCI Slot 3 routes CDAB + Package() { 0x0002ffff, 0, 0, 18}, + Package() { 0x0002ffff, 1, 0, 19}, + Package() { 0x0002ffff, 2, 0, 16}, + Package() { 0x0002ffff, 3, 0, 17}, + + // PCI Slot 4 routes ABCD + Package() { 0x0003ffff, 0, 0, 16}, + Package() { 0x0003ffff, 1, 0, 17}, + Package() { 0x0003ffff, 2, 0, 18}, + Package() { 0x0003ffff, 3, 0, 19}, + + // PCI Slot 5 routes ABCD + Package() { 0x0004ffff, 0, 0, 16}, + Package() { 0x0004ffff, 1, 0, 17}, + Package() { 0x0004ffff, 2, 0, 18}, + Package() { 0x0004ffff, 3, 0, 19}, + + // PCI Slot 6 routes BCDA + Package() { 0x0005ffff, 0, 0, 17}, + Package() { 0x0005ffff, 1, 0, 18}, + Package() { 0x0005ffff, 2, 0, 19}, + Package() { 0x0005ffff, 3, 0, 16}, + + // FIXME: what's this supposed to mean? (adopted from ich7) + //Package() { 0x0008ffff, 0, 0, 20}, + }) +} Else { + Return (Package() { + // PCI Slot 1 routes ABCD + Package() { 0x0000ffff, 0, _SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0000ffff, 1, _SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0000ffff, 2, _SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0000ffff, 3, _SB.PCI0.LPCB.LNKD, 0}, + + // PCI Slot 2 routes BCDA + Package() { 0x0001ffff, 0, _SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0001ffff, 1, _SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0001ffff, 2, _SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0001ffff, 3, _SB.PCI0.LPCB.LNKA, 0}, + + // PCI Slot 3 routes CDAB + Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0002ffff, 1, _SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0002ffff, 2, _SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0002ffff, 3, _SB.PCI0.LPCB.LNKB, 0}, + + // PCI Slot 4 routes ABCD + Package() { 0x0003ffff, 0, _SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0003ffff, 1, _SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0003ffff, 2, _SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0003ffff, 3, _SB.PCI0.LPCB.LNKD, 0}, + + // PCI Slot 5 routes ABCD + Package() { 0x0004ffff, 0, _SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0004ffff, 1, _SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0004ffff, 2, _SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0004ffff, 3, _SB.PCI0.LPCB.LNKD, 0}, + + // PCI Slot 6 routes BCDA + Package() { 0x0005ffff, 0, _SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0005ffff, 1, _SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0005ffff, 2, _SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0005ffff, 3, _SB.PCI0.LPCB.LNKA, 0}, + + // FIXME + // Package() { 0x0008ffff, 0, _SB.PCI0.LPCB.LNKE, 0}, + }) +} diff --git a/src/mainboard/toshiba/a300-1me/acpi/mainboard.asl b/src/mainboard/toshiba/a300-1me/acpi/mainboard.asl new file mode 100644 index 0000000..2f0c927 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/acpi/mainboard.asl @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (LID0) +{ + Name(_HID, EisaId("PNP0C0D")) + Method(_LID, 0) + { + Return (_SB.PCI0.LPCB.EC0.LIDC) + } +} + +Device (SLPB) +{ + Name(_HID, EisaId("PNP0C0E")) +} + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) + + // Wake + Name(_PRW, Package(){0x18, 0x04}) +} + +//#include "acpi/battery.asl" diff --git a/src/mainboard/toshiba/a300-1me/acpi/platform.asl b/src/mainboard/toshiba/a300-1me/acpi/platform.asl new file mode 100644 index 0000000..f9adffa --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/acpi/platform.asl @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + // Call a trap so SMI can prepare for Sleep as well. + // TRAP(0x55) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + + Return(Package(){0,0}) +} diff --git a/src/mainboard/toshiba/a300-1me/acpi/superio.asl b/src/mainboard/toshiba/a300-1me/acpi/superio.asl new file mode 100644 index 0000000..48630b0 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/acpi/superio.asl @@ -0,0 +1 @@ +// dummy diff --git a/src/mainboard/toshiba/a300-1me/acpi/thermal.asl b/src/mainboard/toshiba/a300-1me/acpi/thermal.asl new file mode 100644 index 0000000..d7f8364 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/acpi/thermal.asl @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Thermal Zone + +Scope (_TZ) +{ + /* degree Celcius to deci-Kelvin (ACPI temperature unit) */ + Method(C2dK, 1) { + Add (2732, Multiply (Arg0, 10), Local0) + Return (Local0) + } + + ThermalZone (THRM) + { + + // FIXME these could/should be read from the + // GNVS area, so they can be controlled by + // coreboot + Name(TC1V, 0x04) + Name(TC2V, 0x03) + Name(TSPV, 0x96) + + // At which temperature should the OS start + // active cooling? + Method (_AC0, 0, Serialized) + { + Return (C2dK(120)) // Value for Rocky + } + + // Critical shutdown temperature + Method (_CRT, 0, Serialized) + { + Return (C2dK(155)) // Value for Rocky + } + + // CPU throttling start temperature + Method (_PSV, 0, Serialized) + { + Return (C2dK(105)) // Value for Rocky + } + + // Get DTS Temperature + Method (_TMP, 0, Serialized) + { + If (_SB.PCI0.LPCB.EC0.ALRC) { + Store(0, _SB.PCI0.LPCB.EC0.ALRC) + Return(_AC0()) + } + + If (_SB.PCI0.LPCB.EC0.ALRL) { + Store(0, THRO) + Store(0, _SB.PCI0.LPCB.EC0.ALRL) + } + + If (_SB.PCI0.LPCB.EC0.ALRH) { + Store(1, THRO) + Store(0, _SB.PCI0.LPCB.EC0.ALRH) + } + + /* vendor BIOS reports 0K if TCPU >= 128 deg C ?!? */ + Return (C2dK(_SB.PCI0.LPCB.EC0.TCPU)) + } + + + // Processors used for active cooling + Method (_PSL, 0, Serialized) + { + If (MPEN) { + Return (Package() {_PR.CP00, _PR.CP01}) + } + Return (Package() {_PR.CP00}) + } + + // TC1 value for passive cooling + Method (_TC1, 0, Serialized) + { + Return (TC1V) + } + + // TC2 value for passive cooling + Method (_TC2, 0, Serialized) + { + Return (TC2V) + } + + // Sampling period for passive cooling + Method (_TSP, 0, Serialized) + { + Return (TSPV) + } + + + } +} diff --git a/src/mainboard/toshiba/a300-1me/acpi_tables.c b/src/mainboard/toshiba/a300-1me/acpi_tables.c new file mode 100644 index 0000000..0716d2d --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/acpi_tables.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <arch/ioapic.h> +#include <arch/acpi.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <southbridge/intel/i82801ix/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + + /* Enable both COM ports */ + //gnvs->cmap = 0x01; + //gnvs->cmbp = 0x01; + +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* LAPIC_NMI */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 0, + MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 1, MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); + + + return current; +} diff --git a/src/mainboard/toshiba/a300-1me/blc.c b/src/mainboard/toshiba/a300-1me/blc.c new file mode 100644 index 0000000..4b6104e --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/blc.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 arthur@aheymans.xyz + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <northbridge/intel/gm45/gm45.h> + +int get_blc_values(const struct blc_pwm_t **entries) +{ + return 0; +} diff --git a/src/mainboard/toshiba/a300-1me/board_info.txt b/src/mainboard/toshiba/a300-1me/board_info.txt new file mode 100644 index 0000000..4ce92d3 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/board_info.txt @@ -0,0 +1 @@ +Category: laptop diff --git a/src/mainboard/toshiba/a300-1me/cmos.layout b/src/mainboard/toshiba/a300-1me/cmos.layout new file mode 100644 index 0000000..d794306 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/cmos.layout @@ -0,0 +1,119 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# 2012 secunet Security Networks AG +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +#400 8 r 0 unused + +# coreboot config options: southbridge +408 1 e 9 sata_mode +#409 7 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +#937 7 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum + +# coreboot config options: northbridge +1000 4 e 10 gfx_uma_size + +#1004 20 r 0 unused + +# RAM initialization internal data +1024 128 r 0 read_training_results + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 AHCI +9 1 Compatible +11 4 32M +11 5 48M +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/toshiba/a300-1me/cstates.c b/src/mainboard/toshiba/a300-1me/cstates.c new file mode 100644 index 0000000..fea9276 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/cstates.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> + +static acpi_cstate_t cst_entries[] = { + { + /* ACPI C1 / CPU C1 */ + 1, 0x01, 1000, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, 1, 0, 0 } + }, + { + /* ACPI C2 / CPU C2 */ + 2, 0x01, 500, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, 1, 0x10, 0 } + }, +}; + +int get_cst_entries(acpi_cstate_t **entries) +{ + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); +} diff --git a/src/mainboard/toshiba/a300-1me/devicetree.cb b/src/mainboard/toshiba/a300-1me/devicetree.cb new file mode 100644 index 0000000..5936104 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/devicetree.cb @@ -0,0 +1,142 @@ +chip northbridge/intel/gm45 + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + device cpu_cluster 0 on + chip cpu/intel/socket_BGA956 + device lapic 0 on end + end + chip cpu/intel/model_1067x + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + # Enable Super LFM + register "slfm" = "1" + + # Enable C5, C6 + register "c5" = "1" + register "c6" = "1" + end + end + + register "pci_mmio_size" = "2048" + + device domain 0 on + subsystemid 0x1179 0xff1e inherit + device pci 00.0 on end # host bridge + device pci 01.0 on end # PEG + device pci 02.0 off # VGA + # ioapic_irq 2 INTA 0x10 + end + device pci 02.1 off end # Display + device pci 03.0 off end # ME + device pci 03.1 off end # ME + device pci 03.2 off end # ME + device pci 03.3 off end # ME + chip southbridge/intel/i82801ix + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + register "gpi8_routing" = "2" + register "gpi7_routing" = "2" + register "gpe0_en" = "0x01800042" + register "gpi1_routing" = "1" + register "alt_gp_smi_en" = "0x0002" + + # Set AHCI mode, enable ports 1 and 2. + register "sata_port_map" = "0x03" + register "sata_clock_request" = "0" + register "sata_traffic_monitor" = "0" + + # Set c-state support + register "c4onc3_enable" = "0" + register "c5_enable" = "1" + register "c6_enable" = "1" + + # Set thermal throttling to 75%. + register "throttle_duty" = "THTL_75_0" + + # Enable PCIe ports 1 and 5 as slots (Mini * PCIe). + # register "pcie_slot_implemented" = "0x11" + # Set power limits to 10 * 10^0 watts. + # Maybe we should set less for Mini PCIe. + # register "pcie_power_limits" = "{ { 10, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 } }" + + device pci 19.0 off end # LAN + device pci 1a.0 on # UHCI + #ioapic_irq 2 INTA 0x10 + end + device pci 1a.1 on # UHCI + #ioapic_irq 2 INTB 0x11 + end + device pci 1a.2 on # UHCI + #ioapic_irq 2 INTC 0x12 + end + device pci 1a.7 on # EHCI + #ioapic_irq 2 INTC 0x12 + end + device pci 1b.0 on # HD Audio + #ioapic_irq 2 INTA 0x10 + end + device pci 1c.0 on # PCIe Port #1 + #ioapic_irq 2 INTA 0x10 + end + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on # PCIe Port #5 + #ioapic_irq 2 INTA 0x10 + #device pci 00.0 on end # Realtek 8168B + end + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on # UHCI + #ioapic_irq 2 INTA 0x10 + end + device pci 1d.1 on # UHCI + #ioapic_irq 2 INTB 0x11 + end + device pci 1d.2 on # UHCI + #ioapic_irq 2 INTC 0x12 + end + device pci 1d.7 on # EHCI + #ioapic_irq 2 INTA 0x10 + end + device pci 1e.0 on # PCI + #device pci 03.0 on # TI Cardbus + #ioapic_irq 2 INTA 0x10 + #end + #device pci 03.1 on # TI Cardbus + #ioapic_irq 2 INTB 0x11 + #end + #device pci 03.2 off end # TI FireWire OHC + #device pci 03.3 off end # unconnected FlashMedia + #device pci 03.4 off end # unconnected SD-Card + end + device pci 1f.0 on # LPC bridge + #chip drivers/generic/ioapic + #register "have_isa_interrupts" = "1" + #register "irq_on_fsb" = "1" + #register "enable_virtual_wire" = "1" + #register "base" = "(void *)0xfec00000" + #device ioapic 2 on end + #end + + # FIXME: WPCE775 support + end + device pci 1f.2 on # SATA/IDE 1 + #ioapic_irq 2 INTB 0x11 + end + device pci 1f.3 on # SMBus + #ioapic_irq 2 INTC 0x12 + end + device pci 1f.5 off end # SATA/IDE 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/toshiba/a300-1me/dsdt.asl b/src/mainboard/toshiba/a300-1me/dsdt.asl new file mode 100644 index 0000000..cf2479a --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/dsdt.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20090419 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/i82801ix/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/platform.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + // mainboard specific devices + //#include "acpi/mainboard.asl" + + #include <cpu/intel/speedstep/acpi/cpu.asl> + + // Thermal Zone + //#include "acpi/thermal.asl" + + Scope (_SB) { + Device (PCI0) + { + #include <northbridge/intel/gm45/acpi/gm45.asl> + #include <southbridge/intel/i82801ix/acpi/ich9.asl> + + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801ix/acpi/sleepstates.asl> +} diff --git a/src/mainboard/toshiba/a300-1me/fadt.c b/src/mainboard/toshiba/a300-1me/fadt.c new file mode 100644 index 0000000..f2b8559 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/fadt.c @@ -0,0 +1,154 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> +#include <version.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = get_acpi_table_revision(FADT); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = asl_revision; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->reserved = 0x00; + fadt->preferred_pm_profile = PM_MOBILE; + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = APM_CNT_PST_CONTROL; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; /* Upper word is reserved and + Linux complains about 32 bit. */ + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = APM_CNT_CST_CONTROL; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 0x39; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x32; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_DOCKING_SUPPORTED | ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + fadt->reset_value = 0x06; + + fadt->x_firmware_ctl_l = 0; /* Set X_FIRMWARE_CTRL only if FACS is */ + fadt->x_firmware_ctl_h = 0; /* above 4GB. If X_FIRMWARE_CTRL is set, */ + /* then FIRMWARE_CTRL must be zero. */ + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 0; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; /* Upper word is reserved and + Linux complains about 32 bit. */ + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 0; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 0; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/toshiba/a300-1me/gpio.c b/src/mainboard/toshiba/a300-1me/gpio.c new file mode 100644 index 0000000..92454cb --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/gpio.c @@ -0,0 +1,208 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NATIVE, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_NATIVE, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_NATIVE, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_NATIVE, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_LOW, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_NATIVE, + .gpio34 = GPIO_MODE_NATIVE, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_NATIVE, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/toshiba/a300-1me/hda_verb.c b/src/mainboard/toshiba/a300-1me/hda_verb.c new file mode 100644 index 0000000..63f37b5 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/hda_verb.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0262, /* Codec Vendor / Device ID: Realtek ALC262 */ + 0x43528986, /* Subsystem ID */ + 0x0000000c, /* Number of entries */ + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x11), S/PDIF-OUT2: not connected */ + AZALIA_PIN_CFG(0, 0x11, 0x411111f0), + /* Pin Complex (NID 0x14), LINE_OUT (port D): Speakers */ + AZALIA_PIN_CFG(0, 0x14, 0x99130110), + /* Pin Complex (NID 0x15), HP_OUT (port A): Head phones */ + AZALIA_PIN_CFG(0, 0x15, 0x0121411f), + /* Pin Complex (NID 0x16), MONO-OUT: not connected */ + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + /* Pin Complex (NID 0x18), MIC1 (port B): Microphone */ + AZALIA_PIN_CFG(0, 0x18, 0x01a19920), + /* Pin Complex (NID 0x19), MIC2 (port F): not connected */ + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + /* Pin Complex (NID 0x1a), LINE1 (port C): Line-In */ + AZALIA_PIN_CFG(0, 0x1a, 0x01813121), + /* Pin Complex (NID 0x1b), LINE2 (port E): MDC */ + AZALIA_PIN_CFG(0, 0x1b, 0x9983012f), + /* Pin Complex (NID 0x1c), CD_IN */ + AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), + /* Pin Complex (NID 0x1d), PCBEEP */ + AZALIA_PIN_CFG(0, 0x1d, 0x4014022d), + /* Pin Complex (NID 0x1e), S/PDIF-OUT: not connected */ + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + /* Pin Complex (NID 0x1f), S/PDIF-IN: not connected */ + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0) +}; + +const u32 pc_beep_verbs[] = { + //0x00170500, /* power up codec */ + //0x01470500, /* power up speakers */ + //0x01470100, /* select lout1 (input 0x0) for speakers */ + //0x01470740, /* enable speakers output */ + //0x00b37517, /* unmute beep (mixer's input 0x5), set amp 0dB */ + //0x00c37100, /* unmute mixer in lout1 (lout1 input 0x1) */ + //0x00c3b015, /* set lout1 output volume -15dB */ + //0x0143b000, /* unmute speakers */ +}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/toshiba/a300-1me/mainboard.c b/src/mainboard/toshiba/a300-1me/mainboard.c new file mode 100644 index 0000000..eb1ae23 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/mainboard.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stdlib.h> +#include <arch/io.h> +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <pc80/keyboard.h> +#include <ec/acpi/ec.h> + +static void ec_setup(void) +{ + /* Thermal limits? Values are from ectool's RAM dump. */ + //ec_write(0xd1, 0x57); /* CPUH */ + //ec_write(0xd2, 0xc9); /* CPUL */ + //ec_write(0xd4, 0x64); /* SYSH */ + //ec_write(0xd5, 0xc9); /* SYSL */ + + //send_ec_command(0x04); /* Set_SMI_Enable */ + //send_ec_command(0xab); /* Set_ACPI_Disable */ + //send_ec_command(0xac); /* Clr_SYS_Flag? well, why not? */ + //send_ec_command(0xad); /* Set_Thml_Value */ +} + +static void mainboard_enable(struct device *dev) +{ + ec_setup(); + /* LCD panel type is SIO GPIO40-43. + It's controlled by a DIP switch but was always + set to 4 while only values of 5 and 6 worked. */ + //install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, (inb(0x60f) & 0x0f) + 1); + + /* We have no driver for the embedded controller since the firmware + does most of the job. Hence, initialize keyboards here. */ + pc_keyboard_init(NO_AUX_DEVICE); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/toshiba/a300-1me/romstage.c b/src/mainboard/toshiba/a300-1me/romstage.c new file mode 100644 index 0000000..dc2b900 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/romstage.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <arch/io.h> +#include <device/pnp_ops.h> +#include <device/pci_ops.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/i82801ix/i82801ix.h> +#include <northbridge/intel/gm45/gm45.h> + +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +void mb_setup_lpc(void) +{ + /* Configure serial IRQs.*/ + pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0); + /* Map COMa on 0x3f8, COMb on 0x2f8. */ + pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010); + /* Enable COMa, COMb, Kbd, SuperIO at 0x2e, MCs at 0x4e and 0x62/66. */ + pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3c03); +} + +void mb_setup_superio(void) +{ + // #FIXME: WPCE775 support +} + +void get_mb_spd_addrmap(u8 *spd_addrmap) +{ + spd_addrmap[0] = 0x50; + spd_addrmap[2] = 0x52; +} diff --git a/src/mainboard/toshiba/a300-1me/smistuff.c b/src/mainboard/toshiba/a300-1me/smistuff.c new file mode 100644 index 0000000..72f1d35 --- /dev/null +++ b/src/mainboard/toshiba/a300-1me/smistuff.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/i82801ix/nvs.h> +#include <southbridge/intel/i82801ix/i82801ix.h> +#include <ec/acpi/ec.h> + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << 1)) { + printk(BIOS_DEBUG, "EC/SMI\n"); + /* TODO */ + } +} + +int mainboard_smi_apmc(u8 apmc) +{ + switch (apmc) { + case APM_CNT_ACPI_ENABLE: + send_ec_command(0x05); /* Set_SMI_Disable */ + send_ec_command(0xaa); /* Set_ACPI_Enable */ + break; + + case APM_CNT_ACPI_DISABLE: + send_ec_command(0x04); /* Set_SMI_Enable */ + send_ec_command(0xab); /* Set_ACPI_Disable */ + break; + } + return 0; +}
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34786 )
Change subject: mb/toshiba: Add A300-1ME ......................................................................
Patch Set 4:
(1 comment)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/34786/3/src/mainboard/toshiba/a300-... File src/mainboard/toshiba/a300-1me/acpi/ich9_pci_irqs.asl:
https://review.coreboot.org/c/coreboot/+/34786/3/src/mainboard/toshiba/a300-... PS3, Line 24: // PCI Slot 1 routes ABCD : Package() { 0x0000ffff, 0, 0, 16}, : Package() { 0x0000ffff, 1, 0, 17}, : Package() { 0x0000ffff, 2, 0, 18}, : Package() { 0x0000ffff, 3, 0, 19}, : : // PCI Slot 2 routes BCDA : Package() { 0x0001ffff, 0, 0, 17}, : Package() { 0x0001ffff, 1, 0, 18}, : Package() { 0x0001ffff, 2, 0, 19}, : Package() { 0x0001ffff, 3, 0, 16}, : : // PCI Slot 3 routes CDAB : Package() { 0x0002ffff, 0, 0, 18}, : Package() { 0x0002ffff, 1, 0, 19}, : Package() { 0x0002ffff, 2, 0, 16}, : Package() { 0x0002ffff, 3, 0, 17}, : : // PCI Slot 4 routes ABCD : Package() { 0x0003ffff, 0, 0, 16}, : Package() { 0x0003ffff, 1, 0, 17}, : Package() { 0x0003ffff, 2, 0, 18}, : Package() { 0x0003ffff, 3, 0, 19}, : : // PCI Slot 5 routes ABCD : Package() { 0x0004ffff, 0, 0, 16}, : Package() { 0x0004ffff, 1, 0, 17}, : Package() { 0x0004ffff, 2, 0, 18}, : Package() { 0x0004ffff, 3, 0, 19}, : : // PCI Slot 6 routes BCDA : Package() { 0x0005ffff, 0, 0, 17}, : Package() { 0x0005ffff, 1, 0, 18}, : Package() { 0x0005ffff, 2, 0, 19}, : Package() { 0x0005ffff, 3, 0, 16}, : : // FIXME: what's this supposed to mean? (adopted from ich7) : //Package() { 0x0008ffff, 0, 0, 20},
This is likely wrong.
Indeed it was. Fixed.
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34786 )
Change subject: mb/toshiba: Add A300-1ME ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34786/4/src/mainboard/toshiba/a300-... File src/mainboard/toshiba/a300-1me/blc.c:
https://review.coreboot.org/c/coreboot/+/34786/4/src/mainboard/toshiba/a300-... PS4, Line 16: #include <stdint.h> why?
https://review.coreboot.org/c/coreboot/+/34786/4/src/mainboard/toshiba/a300-... File src/mainboard/toshiba/a300-1me/mainboard.c:
https://review.coreboot.org/c/coreboot/+/34786/4/src/mainboard/toshiba/a300-... PS4, Line 16: #include <stdint.h> : #include <stdlib.h> : #include <arch/io.h> : #include <device/device.h> : #include <drivers/intel/gma/int15.h> : #include <pc80/keyboard.h> : #include <ec/acpi/ec.h> please clean
https://review.coreboot.org/c/coreboot/+/34786/4/src/mainboard/toshiba/a300-... File src/mainboard/toshiba/a300-1me/romstage.c:
https://review.coreboot.org/c/coreboot/+/34786/4/src/mainboard/toshiba/a300-... PS4, Line 18: #include <arch/io.h> : #include <device/pnp_ops.h> : #include <device/pci_ops.h> : #include <southbridge/intel/common/gpio.h> : #include <southbridge/intel/i82801ix/i82801ix.h> : #include <northbridge/intel/gm45/gm45.h> please clean
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34786 )
Change subject: mb/toshiba: Add A300-1ME ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34786/4/src/mainboard/toshiba/a300-... File src/mainboard/toshiba/a300-1me/romstage.c:
https://review.coreboot.org/c/coreboot/+/34786/4/src/mainboard/toshiba/a300-... PS4, Line 18: #include <arch/io.h> : #include <device/pnp_ops.h> : #include <device/pci_ops.h> : #include <southbridge/intel/common/gpio.h> : #include <southbridge/intel/i82801ix/i82801ix.h> : #include <northbridge/intel/gm45/gm45.h>
please clean
I'll clean those once I make the EC work. See FIXMEs below
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34786
to look at the new patch set (#5).
Change subject: mb/toshiba: Add A300-1ME ......................................................................
mb/toshiba: Add A300-1ME
Mainboard real name (to find schematics) is Inventec Potomac 10G. Vendor firmware is InsydeH20 EFI Rev. 3.5 and shows postcodes on LPC.
This thing is a PM45/ICH9M notebook with a WPCE775 EC. It usually boots from LPC via EC, but also has space for another flash chip, directly attached to SPI.
Working: - usbdebug with FT2232H (left side, the non-eSATA USB port) - postcodes via LPC (debug card on WLAN card slot) with vendor firmware coreboot may not be printing any postcodes on this platform, so this may explain why postcodes don't show with coreboot. But the hw works. - running coreboot off the ICH SPI flash chip - fan runs at a high speed by default (no risk of overheating) - dedicated GPU with VBIOS lightup - minimum coreboot cold boot time delta is under 250 ms - the damn IRQs are not a nightmare anymore - the integrated keyboard and touchpad work just fine
Notes: - With gm45 ddr2 raminit patches in, the board boots to Linux fine - The watchdog that was tripping before is the ICH watchdog. It does not trip once raminit passes. - To extract the VBIOS, this is known to work: sudo cat /sys/devices/pci0000:00/0000:00:01.0/0000:01:00.0/rom > pci1002,95c4.rom
Not working: - Embedded controller, as usual... <insert insults here>
Change-Id: Ifcdfadd2506962bc797b174b4d656e9201f7a40d Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/toshiba/Kconfig A src/mainboard/toshiba/Kconfig.name A src/mainboard/toshiba/a300-1me/Kconfig A src/mainboard/toshiba/a300-1me/Kconfig.name A src/mainboard/toshiba/a300-1me/Makefile.inc A src/mainboard/toshiba/a300-1me/acpi/ec.asl A src/mainboard/toshiba/a300-1me/acpi/ich9_pci_irqs.asl A src/mainboard/toshiba/a300-1me/acpi/platform.asl A src/mainboard/toshiba/a300-1me/acpi/superio.asl A src/mainboard/toshiba/a300-1me/acpi_tables.c A src/mainboard/toshiba/a300-1me/blc.c A src/mainboard/toshiba/a300-1me/board_info.txt A src/mainboard/toshiba/a300-1me/cmos.layout A src/mainboard/toshiba/a300-1me/cstates.c A src/mainboard/toshiba/a300-1me/devicetree.cb A src/mainboard/toshiba/a300-1me/dsdt.asl A src/mainboard/toshiba/a300-1me/fadt.c A src/mainboard/toshiba/a300-1me/gpio.c A src/mainboard/toshiba/a300-1me/hda_verb.c A src/mainboard/toshiba/a300-1me/mainboard.c A src/mainboard/toshiba/a300-1me/romstage.c 21 files changed, 987 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/34786/5
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34786 )
Change subject: mb/toshiba: Add A300-1ME ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34786/5/src/mainboard/toshiba/a300-... File src/mainboard/toshiba/a300-1me/acpi/platform.asl:
https://review.coreboot.org/c/coreboot/+/34786/5/src/mainboard/toshiba/a300-... PS5, Line 15: */ Just a reminder to use SPDX license headers.
Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34786
to look at the new patch set (#6).
Change subject: mb/toshiba: Add A300-1ME ......................................................................
mb/toshiba: Add A300-1ME
Mainboard real name (to find schematics) is Inventec Potomac 10G. Vendor firmware is InsydeH20 EFI Rev. 3.5 and shows postcodes on LPC.
This thing is a PM45/ICH9M notebook with a WPCE775 EC. It usually boots from LPC via EC, but also has space for another flash chip, directly attached to SPI.
Working: - usbdebug with FT2232H (left side, the non-eSATA USB port) - postcodes via LPC (debug card on WLAN card slot) with vendor firmware coreboot may not be printing any postcodes on this platform, so this may explain why postcodes don't show with coreboot. But the hw works. - running coreboot off the ICH SPI flash chip - fan runs at a high speed by default (no risk of overheating) - dedicated GPU with VBIOS lightup - minimum coreboot cold boot time delta is under 250 ms - the damn IRQs are not a nightmare anymore - the integrated keyboard and touchpad work just fine
Notes: - With gm45 ddr2 raminit patches in, the board boots to Linux fine - The watchdog that was tripping before is the ICH watchdog. It does not trip once raminit passes. - To extract the VBIOS, this is known to work: sudo cat /sys/devices/pci0000:00/0000:00:01.0/0000:01:00.0/rom > pci1002,95c4.rom
Not working: - Embedded controller, as usual... <insert insults here>
Change-Id: Ifcdfadd2506962bc797b174b4d656e9201f7a40d Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/toshiba/Kconfig A src/mainboard/toshiba/Kconfig.name A src/mainboard/toshiba/a300-1me/Kconfig A src/mainboard/toshiba/a300-1me/Kconfig.name A src/mainboard/toshiba/a300-1me/Makefile.inc A src/mainboard/toshiba/a300-1me/acpi/ec.asl A src/mainboard/toshiba/a300-1me/acpi/ich9_pci_irqs.asl A src/mainboard/toshiba/a300-1me/acpi/platform.asl A src/mainboard/toshiba/a300-1me/acpi/superio.asl A src/mainboard/toshiba/a300-1me/acpi_tables.c A src/mainboard/toshiba/a300-1me/blc.c A src/mainboard/toshiba/a300-1me/board_info.txt A src/mainboard/toshiba/a300-1me/cmos.layout A src/mainboard/toshiba/a300-1me/cstates.c A src/mainboard/toshiba/a300-1me/devicetree.cb A src/mainboard/toshiba/a300-1me/dsdt.asl A src/mainboard/toshiba/a300-1me/fadt.c A src/mainboard/toshiba/a300-1me/gpio.c A src/mainboard/toshiba/a300-1me/hda_verb.c A src/mainboard/toshiba/a300-1me/mainboard.c A src/mainboard/toshiba/a300-1me/romstage.c 21 files changed, 1,297 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/34786/6
-
Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)
-
Paul Menzel (Code Review)