[S] Change in coreboot[master]: soc/amd/*/include/data_fabric: rename D18F0_DRAM_* to DF_DRAM_*

[Felix Held (Code Review)]

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier.

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76889?usp=email )

Change subject: soc/amd/*/include/data_fabric: rename D18F0_DRAM_* to DF_DRAM_*
......................................................................

soc/amd/*/include/data_fabric: rename D18F0_DRAM_* to DF_DRAM_*

Now that the data fabric PCI device functions are included in the
register definitions, the remaining data fabric device function numbers
can be dropped form the define names.

Signed-off-by: Felix Held 
Change-Id: I1a26402b8078d288a7e32c1668591d001fa3ede9
---
M src/soc/amd/picasso/agesa_acpi.c
M src/soc/amd/picasso/include/soc/data_fabric.h
2 files changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/76889/1

diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c
index ed0b456..9ee977f 100644
--- a/src/soc/amd/picasso/agesa_acpi.c
+++ b/src/soc/amd/picasso/agesa_acpi.c
@@ -85,7 +85,7 @@
    		}

if (dram_base_reg & DRAM_BASE_HOLE_EN) {
-				dram_hole_ctl = data_fabric_read32(D18F0_DRAM_HOLE_CTL,
+				dram_hole_ctl = data_fabric_read32(DF_DRAM_HOLE_CTL,
    							       IOMS0_FABRIC_ID);
    			hole_base = (dram_hole_ctl & DRAM_HOLE_CTL_BASE);
    			size_below_hole = hole_base - memory_base;
diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h
index 93d3239..5926e49d 100644
--- a/src/soc/amd/picasso/include/soc/data_fabric.h
+++ b/src/soc/amd/picasso/include/soc/data_fabric.h
@@ -50,12 +50,12 @@
 #define D18F0_VGAEN			DF_REG_ID(0, 0x80)
 #define   VGA_ADDR_ENABLE		BIT(0)

-#define D18F0_DRAM_HOLE_CTL		DF_REG_ID(0, 0x104)
+#define DF_DRAM_HOLE_CTL		DF_REG_ID(0, 0x104)
 #define   DRAM_HOLE_CTL_VALID		BIT(0)
 #define   DRAM_HOLE_CTL_BASE_SHFT	24
 #define   DRAM_HOLE_CTL_BASE		(0xff << DRAM_HOLE_CTL_BASE_SHFT)

-#define D18F0_DRAM_BASE0		DF_REG_ID(0, 0x110)
+#define DF_DRAM_BASE0		DF_REG_ID(0, 0x110)
 #define   DRAM_BASE_REG_VALID		BIT(0)
 #define   DRAM_BASE_HOLE_EN		BIT(1)
 #define   DRAM_BASE_INTLV_CH_SHFT	4
@@ -65,7 +65,7 @@
 #define   DRAM_BASE_ADDR_SHFT		12
 #define   DRAM_BASE_ADDR		(0xfffff << DRAM_BASE_ADDR_SHFT)

-#define D18F0_DRAM_LIMIT0			DF_REG_ID(0, 0x114)
+#define DF_DRAM_LIMIT0			DF_REG_ID(0, 0x114)
 #define   DRAM_LIMIT_DST_ID_SHFT		0
 #define   DRAM_LIMIT_DST_ID			(0xff << DRAM_LIMIT_DST_ID_SHFT)
 #define   DRAM_LIMIT_INTLV_NUM_SOCK_SHFT	8
@@ -78,8 +78,8 @@
 #define PICASSO_NUM_DRAM_REG		2

#define DF_DRAM_BASE(dram_map_pair)	((dram_map_pair) * 2 * sizeof(uint32_t) \
-						+ D18F0_DRAM_BASE0)
+						+ DF_DRAM_BASE0)
 #define DF_DRAM_LIMIT(dram_map_pair)	((dram_map_pair) * 2 * sizeof(uint32_t) \
-						+ D18F0_DRAM_LIMIT0)
+						+ DF_DRAM_LIMIT0)

#endif /* AMD_PICASSO_DATA_FABRIC_H */