EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
mb/google/brya: Initiate peripheral buses
Initiate peripheral buses based on latest schematic.
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I3a828bfb3ba4ee9a9b41cd4e83701672e5ef85bf --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 115 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/48295/1
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 479a7ee..00bb4c3 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -3,6 +3,121 @@ device lapic 0 on end end
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # USB2_C1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # USB2_C2 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + + # Enable WLAN PCIE 5 using clk 2 + register "PcieRpEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieClkSrcUsage[2]" = "5" + register "PcieClkSrcClkReq[2]" = "2" + + # Enable WWAN PCIE 6 using clk 5 + register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + register "PcieClkSrcUsage[5]" = "6" + register "PcieClkSrcClkReq[5]" = "5" + + # Enable SD Card PCIE 8 using clk 3 + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + register "PcieRpHotPlug[7]" = "1" + register "PcieClkSrcUsage[3]" = "7" + register "PcieClkSrcClkReq[3]" = "3" + + # Enable NVMe PCIE 9 using clk 1 + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "1" + register "PcieClkSrcUsage[1]" = "9" + register "PcieClkSrcClkReq[1]" = "1" + + + # Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality + register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[8]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[9]" = "PCIE_CLK_NOTUSED" + # SRCCLKREQ9B??? + register "PcieClkSrcUsage[10]" = "PCIE_CLK_NOTUSED" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 1, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 1, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | SAR0 | + #| I2C3 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C4 | CAM | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on device ref igpu on end device ref dtt on end @@ -30,7 +145,6 @@ device ref pcie_rp8 on end #PCIE8 SD card device ref pcie_rp9 on end #PCIE9-12 SSD device ref uart0 on end - device ref gspi0 on end device ref gspi1 on end device ref pch_espi on chip ec/google/chromeec
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 2:
@Subrata, I found fspUpd has PcieClkSrcUsage[18], and schematic has 0-9B. Is 9B map to PcieClkSrcUsage[10]?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 2:
Patch Set 2:
@Subrata, I found fspUpd has PcieClkSrcUsage[18],
Its for unified FSP between ADL-S and P, thats the reason might be but you don't need more than 7 i believe
and schematic has 0-9B. Is 9B map to PcieClkSrcUsage[10]?
what is 9B ?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2:
@Subrata, I found fspUpd has PcieClkSrcUsage[18],
Its for unified FSP between ADL-S and P, thats the reason might be but you don't need more than 7 i believe
and schematic has 0-9B. Is 9B map to PcieClkSrcUsage[10]?
what is 9B ?
GPP_A12/SATAXPCIE1/SATAGP1/SRCCLKREQ9B#
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2:
Patch Set 2:
@Subrata, I found fspUpd has PcieClkSrcUsage[18],
Its for unified FSP between ADL-S and P, thats the reason might be but you don't need more than 7 i believe
and schematic has 0-9B. Is 9B map to PcieClkSrcUsage[10]?
what is 9B ?
GPP_A12/SATAXPCIE1/SATAGP1/SRCCLKREQ9B#
looks like you have CLK REQ 9 so, PcieClkSrcUsage[9] but need to verify ur CLKSRC.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2:
Patch Set 2:
Patch Set 2:
@Subrata, I found fspUpd has PcieClkSrcUsage[18],
Its for unified FSP between ADL-S and P, thats the reason might be but you don't need more than 7 i believe
and schematic has 0-9B. Is 9B map to PcieClkSrcUsage[10]?
what is 9B ?
GPP_A12/SATAXPCIE1/SATAGP1/SRCCLKREQ9B#
looks like you have CLK REQ 9 so, PcieClkSrcUsage[9] but need to verify ur CLKSRC.
GPP_E0/SATAXPCIE0/SATAGP0/SRCCLKREQ9# This is confused because the pin is different.. Not quite understand it. Both map the same ClkSrc?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... PS2, Line 33: register "PcieClkSrcUsage[3]" = "7" Need change to 4 here.. it's a trap lol. "PcieClkSrcUsage[4]" = "7" "PcieClkSrcClkReq[3]" = "4"
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... PS2, Line 33: register "PcieClkSrcUsage[3]" = "7"
Need change to 4 here.. it's a trap lol. […]
Can we use enums for all these fields rather than assigning magic values. I find it confusing always to read the numbers and determine where we need -1/+1 or treat it as is.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... PS2, Line 33: register "PcieClkSrcUsage[3]" = "7"
Can we use enums for all these fields rather than assigning magic values. […]
I don't know why schematic shift the clksrc. Ideal is same clkreq with same clksrc.. then we don't bother the mapping.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... PS2, Line 33: register "PcieClkSrcUsage[3]" = "7"
I don't know why schematic shift the clksrc. Ideal is same clkreq with same clksrc.. […]
I think we can use a structure for this but need to rewrite the fsp_param. What do you think? This is pretty like IBV bios define in config file. And we don't care about the detail just refer the schematic to fill it.
struct { pcie_port, ex:7 clksrc, ex:4 clkreq, ex:3 } pcie_t;
PcieRpEnable[pcie_port] = 1 PcieRpLtrEnable[pcie_port] = 1 PcieClkSrcClkReq[clkreq] = clksrc PcieClkSrcUsage[clksrc] = pcie_port
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... PS2, Line 33: register "PcieClkSrcUsage[3]" = "7"
I think we can use a structure for this but need to rewrite the fsp_param. […]
+1 to your struct Eric
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... PS2, Line 33: register "PcieClkSrcUsage[3]" = "7"
+1 to your struct Eric
Yeah, I like the idea of having a separate config structure for PCIe RPs rather than using the same UPD formats as FSP. SoC code can handle the FSP UPD set up using this config structure.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... PS2, Line 33: register "PcieClkSrcUsage[3]" = "7"
Yeah, I like the idea of having a separate config structure for PCIe RPs rather than using the same […]
@Subrata, what do you think about this? If you agree, we can start to do it and discuss the better way.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... PS2, Line 33: register "PcieClkSrcUsage[3]" = "7"
@Subrata, what do you think about this? If you agree, we can start to do it and discuss the better w […]
Yes, echo to what Furquan and Tim said. lets do something that like
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... PS2, Line 33: register "PcieClkSrcUsage[3]" = "7"
Yes, echo to what Furquan and Tim said. […]
SG, I will push the CL for this :) Then we can discuss there.
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48295
to look at the new patch set (#3).
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
mb/google/brya: Initiate peripheral buses
Initiate peripheral buses based on latest schematic.
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I3a828bfb3ba4ee9a9b41cd4e83701672e5ef85bf --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 107 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/48295/3
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 3:
(1 comment)
Looks better now.
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48295/2/src/mainboard/google/brya/v... PS2, Line 33: register "PcieClkSrcUsage[3]" = "7"
SG, I will push the CL for this :) Then we can discuss there.
Done
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 3:
Do we need to enable DCI usb port in device tree? I think we can just set in ME right? I leave it empty here.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 3: Code-Review+2
Patch Set 3:
Do we need to enable DCI usb port in device tree? I think we can just set in ME right? I leave it empty here.
I don't think we need it here, but not sure
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
mb/google/brya: Initiate peripheral buses
Initiate peripheral buses based on latest schematic.
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I3a828bfb3ba4ee9a9b41cd4e83701672e5ef85bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/48295 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 107 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 479a7ee..96e0a9d 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -3,6 +3,113 @@ device lapic 0 on end end
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # USB2_C1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # USB2_C2 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + + # Enable WLAN PCIE 5 using clk 2 + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_ENABLED, + }" + + # Enable WWAN PCIE 6 using clk 5 + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_ENABLED, + }" + + # Enable SD Card PCIE 8 using clk 3 + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_ENABLED | PCIE_RP_HOTPLUG_ENABLED | PCIE_RP_LTR_ENABLED, + }" + + # Enable NVMe PCIE 9 using clk 1 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_ENABLED | PCIE_RP_LTR_ENABLED, + }" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 1, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 1, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | SAR0 | + #| I2C3 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C4 | CAM | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on device ref igpu on end device ref dtt on end @@ -30,7 +137,6 @@ device ref pcie_rp8 on end #PCIE8 SD card device ref pcie_rp9 on end #PCIE9-12 SSD device ref uart0 on end - device ref gspi0 on end device ref gspi1 on end device ref pch_espi on chip ec/google/chromeec
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 5:
hmmm, this is not ready since the before revise PCIE config still under review... We need revert this or buildbot might crash...
Felix Singer has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/48295 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
-
EricR Lai (Code Review) -
Felix Singer (Code Review)
-
Furquan Shaikh (Code Review)
-
Hung-Te Lin (Code Review)
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Subrata Banik (Code Review)
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Tim Wawrzynczak (Code Review)