Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu.
Hello Chen, Gang C,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/81318?usp=email
to review the following change.
Change subject: soc/intel/xeon_sp/gnr: Add IIO config utils ......................................................................
soc/intel/xeon_sp/gnr: Add IIO config utils
GraniteRapids boards should use _IIO_PE_CFG_STRUCT_BEGIN() to define IIO configurations and invokes soc_config_iio() to apply the settings.
Change-Id: If7146761db6f73a0c4b0d31b010c0d30a42bf690 Signed-off-by: Gang Chen gang.c.chen@intel.com Signed-off-by: Shuo Liu shuo.liu@intel.com --- M src/soc/intel/xeon_sp/gnr/Makefile.inc A src/soc/intel/xeon_sp/gnr/include/soc/iio.h A src/soc/intel/xeon_sp/gnr/soc_iio.c 3 files changed, 176 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/81318/1
diff --git a/src/soc/intel/xeon_sp/gnr/Makefile.inc b/src/soc/intel/xeon_sp/gnr/Makefile.inc index 3d1880d..7246d7e 100644 --- a/src/soc/intel/xeon_sp/gnr/Makefile.inc +++ b/src/soc/intel/xeon_sp/gnr/Makefile.inc @@ -9,7 +9,7 @@ subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/intel/microcode
-romstage-y += romstage.c soc_util.c soc_pmutil.c +romstage-y += romstage.c soc_util.c soc_pmutil.c soc_iio.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c soc_pmutil.c diff --git a/src/soc/intel/xeon_sp/gnr/include/soc/iio.h b/src/soc/intel/xeon_sp/gnr/include/soc/iio.h new file mode 100644 index 0000000..c7fed3d --- /dev/null +++ b/src/soc/intel/xeon_sp/gnr/include/soc/iio.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_IIO_H_ +#define _SOC_IIO_H_ + +#include <soc/soc_util.h> + +#include <fsp/util.h> +#include <IioPcieConfigUpd.h> + +typedef struct { + // + // setting ups for PCIE_PORT_ENTERPRISE_CONFIG + // + uint8_t vpp_address; // SMBUS address of IO expander which provides VPP register + uint8_t vpp_port; // Port or bank on IoExpander which provides VPP register + uint8_t vpp_mux_address; // SMBUS address of MUX used to access VPP + uint8_t vpp_mux_channel; // Channel of the MUX used to access VPP + + uint8_t slot_eip:1; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17) + uint8_t slot_hps:1; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5) + uint8_t slot_pind:1; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4) + uint8_t slot_aind:1; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3) + uint8_t slot_pctl:1; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B1) + uint8_t slot_abtn:1; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0) + uint8_t slot_rsvd:2; // Reserved + + uint8_t vpp_enabled:1; // If VPP is supported on given port + uint8_t vpp_exp_type:1; // IO Expander type used for VPP (see IIO_VPP_EXPANDER_TYPE for values definitions) + + // + // setting ups for IIO_PCIE_PORT_CONFIG + // + uint8_t slot_implemented:1; + uint8_t reserved:4; + + // + // setting ups for PCIE_PORT_COMMON_CONFIG + // + uint16_t hot_plug:1; // If hotplug is supported on slot connected to this port + uint16_t mrl_sensor_present:1; // If MRL is present on slot connected to this port + uint16_t slot_power_limit_scale:2; // Slot Power Scale for slot connected to this port + uint16_t slot_power_limit_value:12; // Slot Power Value for slot connected to this port + + uint16_t physical_slot_number; // Slot number for slot connected to this port +} iio_port_config; + +typedef struct { + uint8_t socket; + IIO_PACKAGE_PE pe; + IIO_BIFURCATION bifurcation; + uint8_t cxl_support:1; + uint8_t reserved:7; + iio_port_config port_config[MAX_IIO_PORTS_PER_STACK]; +} iio_pe_config; + +/* + * _IIO_PE_CFG_STRUCT_BEGIN(socket, pe, bif, cxl) { + * _IIO_PORT_CFG_STRUCT(vaddr vport vmuxa vmuxc + * slteip slthpss sltpip sltaip sltpcp sltabp + * vppen vppex sltimp hotp mrlsp sltpls sltplv phys) + * _IIO_PORT_CFG_STRUCT(..) + * ... + * _IIO_PORT_CFG_STRUCT(..) //MAX_IIO_PORTS_PER_STACK port configs + * } + */ + +#define PE_TYPE_CXL 1 +#define PE_TYPE_PCIE 0 + +#define _IIO_PE_CFG_STRUCT_BEGIN(s, p, bif, cxl) {\ + .socket = s,\ + .pe = p,\ + .bifurcation = bif,\ + .cxl_support = cxl,\ + .reserved = 0,\ + .port_config = + +#define _IIO_PE_CFG_STRUCT_END } + +#define _IIO_PORT_CFG_STRUCT(vaddr, vport, vmuxa, vmuxc,\ + rsv1, rsv2, rsv3, rsv4,\ + slteip, slthpss, sltpip, sltaip, sltpcp, sltabp,\ + vppen, vppex,\ + rsv5, sltimp, hotp, mrlsp, sltpls, sltplv, phys) {\ + .vpp_address = vaddr,\ + .vpp_port = vport,\ + .vpp_mux_address = vmuxa,\ + .vpp_mux_channel = vmuxc,\ + .slot_eip = slteip,\ + .slot_hps = slthpss,\ + .slot_pind = sltpip,\ + .slot_aind = sltaip,\ + .slot_pctl = sltpcp,\ + .slot_abtn = sltabp,\ + .slot_rsvd = 0,\ + .vpp_enabled = vppen,\ + .vpp_exp_type = vppex,\ + .slot_implemented = sltimp,\ + .reserved = 0,\ + .hot_plug = hotp,\ + .mrl_sensor_present = mrlsp,\ + .slot_power_limit_scale = sltpls,\ + .slot_power_limit_value = sltplv,\ + .physical_slot_number = phys\ +} + +void soc_config_iio_pe_ports(FSPM_UPD *mupd, const iio_pe_config *config_table, int num_entries); + +#endif /* _SOC_IIO_H_ */ diff --git a/src/soc/intel/xeon_sp/gnr/soc_iio.c b/src/soc/intel/xeon_sp/gnr/soc_iio.c new file mode 100644 index 0000000..3954366 --- /dev/null +++ b/src/soc/intel/xeon_sp/gnr/soc_iio.c @@ -0,0 +1,65 @@ + /* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fsp/soc_binding.h> +#include <soc/iio.h> +#include <string.h> + +static IIO_BOARD_SETTINGS_HOB iio_upd_hob; + +void soc_config_iio_pe_ports(FSPM_UPD *mupd, const iio_pe_config *config_table, int num_entries) +{ + int i; + uint8_t socket, pe, port; + + const iio_pe_config *board_pe_config; + const iio_port_config *board_port_config; + + IIO_BOARD_SETTINGS_PER_PE *upd_pe_config; + IIO_BOARD_SETTINGS_PER_PORT *upd_port_config; + + memset(&iio_upd_hob, 0, sizeof(iio_upd_hob)); + + for (i = 0; i < num_entries; i++) { + board_pe_config = &config_table[i]; + socket = board_pe_config->socket; + pe = board_pe_config->pe; + + upd_pe_config = &(iio_upd_hob.Socket[socket].Pe[pe]); + + if ((socket >= MAX_SOCKET) || (pe >= MAX_IIO_PCIE_PER_SOCKET)) + continue; + + for (port = 0; port < MAX_IIO_PORTS_PER_STACK; port++) { + upd_port_config = &(upd_pe_config->Port[port]); + board_port_config = &(board_pe_config->port_config[port]); + + upd_pe_config->Bifurcation = board_pe_config->bifurcation; + upd_pe_config->CxlSupportInUba = board_pe_config->cxl_support; + + upd_port_config->Vpp.Address = board_port_config->vpp_address; + upd_port_config->Vpp.Port = board_port_config->vpp_port; + upd_port_config->Vpp.MuxAddress = board_port_config->vpp_mux_address; + upd_port_config->Vpp.MuxChannel = board_port_config->vpp_mux_channel; + + upd_port_config->Slot.Eip = board_port_config->slot_eip; + upd_port_config->Slot.HotPlugSurprise = board_port_config->slot_hps; + upd_port_config->Slot.PowerInd = board_port_config->slot_pind; + upd_port_config->Slot.AttentionInd = board_port_config->slot_aind; + upd_port_config->Slot.PowerCtrl = board_port_config->slot_pctl; + upd_port_config->Slot.AttentionBtn = board_port_config->slot_abtn; + + upd_port_config->VppEnabled = board_port_config->vpp_enabled; + upd_port_config->VppExpType = board_port_config->vpp_exp_type; + + upd_port_config->SlotImplemented = board_port_config->slot_implemented; + upd_port_config->HotPlug = board_port_config->hot_plug; + upd_port_config->MrlSensorPresent = board_port_config->mrl_sensor_present; + upd_port_config->SlotPowerLimitScale = board_port_config->slot_power_limit_scale; + upd_port_config->SlotPowerLimitValue = board_port_config->slot_power_limit_value; + upd_port_config->PhysicalSlotNumber = board_port_config->physical_slot_number; + } + } + + mupd->FspmConfig.IioBoardSettingsHobPtr = (UINT32)&iio_upd_hob; + mupd->FspmConfig.IioBoardSettingsHobLength = sizeof(iio_upd_hob); +}
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Shuo Liu (Code Review)