New patch to review for coreboot: armv7: Word-sized memory operations for 32 bit read/write

[Paul Kocialkowski]

Paul Kocialkowski ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11698

-gerrit

commit f0e12cde71595b828e2a1ccb0438177dee66d606
Author: Paul Kocialkowski 
Date:   Tue Sep 22 22:16:33 2015 +0200

armv7: Word-sized memory operations for 32 bit read/write

Some registers only allow word-sized operations and will cause a data fault when
    accessed with byte-sized operations. However, the compiler may or may not break
    a 32 bit operation into smaller (byte-sized) chunks. Thus, we need to reliably
    perform word-sized operations for 32 bit read/write.

This is particularly the case on the rk3288 SRAM registers, where the watchdog
    tombstone is stored. Moving to GCC 5.2.0 introduced a change of strategy in the
    compiler, where a 32 bit read would be broken into byte-sized chunks, which
    caused a data fault when accessing the watchdog tombstone register.

Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede
    Signed-off-by: Paul Kocialkowski 
---
 src/arch/arm/include/armv7/arch/io.h | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/arch/arm/include/armv7/arch/io.h b/src/arch/arm/include/armv7/arch/io.h
index 9d06003..8983a66 100644
--- a/src/arch/arm/include/armv7/arch/io.h
+++ b/src/arch/arm/include/armv7/arch/io.h
@@ -41,8 +41,11 @@ static inline uint16_t read16(const void *addr)

static inline uint32_t read32(const void *addr)
 {
+	uint32_t val = 0;
+
    dmb();
-	return *(volatile uint32_t *)addr;
+	asm volatile ("ldr %0, [%1, #0]" : "=r" (val) : "r" (addr) : "memory");
+	return val;
 }

static inline void write8(void *addr, uint8_t val)
@@ -62,7 +65,7 @@ static inline void write16(void *addr, uint16_t val)
 static inline void write32(void *addr, uint32_t val)
 {
    dmb();
-	*(volatile uint32_t *)addr = val;
+	asm volatile ("str %0, [%1, #0]" : : "r" (val), "r" (addr) : "memory");
    dmb();
 }