Change in coreboot[master]: [WIP] soc/intel: Use symbols for CAR MTRR setup

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41822 )

Change subject: [WIP] soc/intel: Use symbols for CAR MTRR setup
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[WIP] soc/intel: Use symbols for CAR MTRR setup

Change-Id: Ie5be3329dd63f59a30964c0f3be33e330863b132
Signed-off-by: Kyösti Mälkki 
---
M src/drivers/intel/fsp1_1/cache_as_ram.S
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
2 files changed, 25 insertions(+), 41 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/41822/1

diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S
index 31c3580..4cf4db0 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.S
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.S
@@ -43,12 +43,14 @@

movl	$MTRR_PHYS_BASE(1), %ecx
    xorl	%edx, %edx
-	movl	$(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
+	movl	$CACHE_ROM_BASE, %eax
+	orl	$MTRR_TYPE_WRPROT, %eax
    wrmsr

movl	$MTRR_PHYS_MASK(1), %ecx
    rdmsr
-	movl	$(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
+	movl	$(~(CACHE_ROM_SIZE - 1)), %eax
+	orl	$MTRR_PHYS_MASK_VALID, %eax
    wrmsr

/* Enable cache */
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 69ed174..09a5753 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -78,54 +78,34 @@

post_code(0x24)

-#if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0)
    /* Configure CAR region as write-back (WB) */
    mov	$MTRR_PHYS_BASE(0), %ecx
-	mov	$CONFIG_DCACHE_RAM_BASE, %eax
+	mov	$_car_mtrr_start, %eax
    or	$MTRR_TYPE_WRBACK, %eax
    xor	%edx,%edx
    wrmsr

/* Configure the MTRR mask for the size region */
    mov	$MTRR_PHYS_MASK(0), %ecx
-	mov	$CONFIG_DCACHE_RAM_SIZE, %eax	/* size mask */
-	dec	%eax
-	not	%eax
-	or	$MTRR_PHYS_MASK_VALID, %eax
-	movl	%esi, %edx	/* edx <- MTRR_PHYS_MASK_HIGH */
-	wrmsr
-#elif (CONFIG_DCACHE_RAM_SIZE == 768 * KiB) /* 768 KiB */
-	/* Configure CAR region as write-back (WB) */
-	mov	$MTRR_PHYS_BASE(0), %ecx
-	mov	$CONFIG_DCACHE_RAM_BASE, %eax
-	or	$MTRR_TYPE_WRBACK, %eax
-	xor	%edx,%edx
-	wrmsr
-
-	mov	$MTRR_PHYS_MASK(0), %ecx
-	mov	$(512 * KiB), %eax	/* size mask */
-	dec	%eax
-	not	%eax
+	mov	$_car_mtrr_mask, %eax	/* size mask */
    or	$MTRR_PHYS_MASK_VALID, %eax
    movl	%esi, %edx	/* edx <- MTRR_PHYS_MASK_HIGH */
    wrmsr

+#if 0
    mov	$MTRR_PHYS_BASE(1), %ecx
-	mov	$(CONFIG_DCACHE_RAM_BASE + 512 * KiB), %eax
+	mov	$_car_mtrr_start_1, %eax
    or	$MTRR_TYPE_WRBACK, %eax
    xor	%edx,%edx
    wrmsr

mov	$MTRR_PHYS_MASK(1), %ecx
-	mov	$(256 * KiB), %eax	/* size mask */
-	dec	%eax
-	not	%eax
+	mov	$_car_mtrr_mask_1, %eax
    or	$MTRR_PHYS_MASK_VALID, %eax
    movl	%esi, %edx	/* edx <- MTRR_PHYS_MASK_HIGH */
    wrmsr
-#else
-#error "DCACHE_RAM_SIZE is not a power of 2 and setup code is missing"
 #endif
+
    post_code(0x25)

/* Enable variable MTRRs */
@@ -206,11 +186,11 @@
    post_code(0x26)

/* Clear the cache memory region. This will also fill up the cache */
-	movl	$CONFIG_DCACHE_RAM_BASE, %edi
-	movl	$CONFIG_DCACHE_RAM_SIZE, %ecx
-	shr	$0x02, %ecx
-	xor	%eax, %eax
    cld
+	xor	%eax, %eax
+	movl	$_car_mtrr_start, %edi
+	movl	$_car_mtrr_size, %ecx
+	shr	$0x02, %ecx
    rep	stosl

post_code(0x27)
@@ -265,7 +245,7 @@

/* Calculate how many bits to be used for CAR */
    xor	%edx, %edx
-	mov	$CONFIG_DCACHE_RAM_SIZE, %eax	/* dividend */
+	mov	$_car_mtrr_size, %eax	/* dividend */
    mov	$CONFIG_CACHE_QOS_SIZE_PER_BIT, %ecx	/* divisor */
    div	%ecx		/* result is in eax */
    mov	%eax, %ecx	/* save to ecx */
@@ -303,11 +283,11 @@
    post_code(0x26)

/* Clear the cache memory region. This will also fill up the cache */
-	movl	$CONFIG_DCACHE_RAM_BASE, %edi
-	movl	$CONFIG_DCACHE_RAM_SIZE, %ecx
-	shr	$0x02, %ecx
-	xor	%eax, %eax
    cld
+	xor	%eax, %eax
+	movl	$_car_mtrr_start, %edi
+	movl	$_car_mtrr_size, %ecx
+	shr	$0x02, %ecx
    rep	stosl

post_code(0x27)
@@ -411,12 +391,14 @@
    xorl	%edx, %edx
    wrmsr

-	movl	$CONFIG_DCACHE_RAM_BASE, %edi
-	movl	$CONFIG_DCACHE_RAM_SIZE, %ecx
-	shr	$0x02, %ecx
-	xor	%eax, %eax
+	/* Clear the cache memory region. This will also fill up the cache */
    cld
+	xor	%eax, %eax
+	movl	$_car_mtrr_start, %edi
+	movl	$_car_mtrr_size, %ecx
+	shr	$0x02, %ecx
    rep	stosl
+
    /*
     * Set IA32_PQR_ASSOC = 0x01
     * At this stage we apply LLC_WAY_MASK_1 to the cache.

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/41822 )

Change subject: [WIP] soc/intel: Use symbols for CAR MTRR setup
......................................................................

Abandoned