Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44817 )
Change subject: util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH ......................................................................
util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH
This patch performs below operations: 1. Remove reserved NR field from Gen 5 onwards SPI programming guide 2. Convert ISL to PSL as applicable for Gen 5 onwards PCH 3. Skip FLMAP2 register dump due to nouniformity since Gen 5 onwards PCH 4. Dump FLILL1 register as applicable for Gen 5 onwards PCH 5. Remove FLPB register as not applicable since Gen 5 PCH
BUG=b:153888802 TEST=Dump FD for Hatch platform as below
ifdtool -d coreboot.rom
PCH Revision: 300 series Cannon Point/ 400 series Ice Point FLMAP0: 0x00040003 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x45100208 PSL: 0x45 FPSBA: 0x100 NM: 2 FMBA: 0x80
FLILL1 0xc7c4b9b7 Invalid Instruction 7: 0xc7 Invalid Instruction 6: 0xc4 Invalid Instruction 5: 0xb9 Invalid Instruction 4: 0xb7
Signed-off-by: Subrata Banik subrata.banik@intel.com Change-Id: I5141ae5dd174659fde5401fac313a701ae4f8f44 --- M util/ifdtool/ifdtool.c 1 file changed, 37 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/44817/1
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index b15b163..4de1205 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -518,6 +518,17 @@
return 0; } + +/* FLMAP0 register bit 24 onwards are reserved from SPT PCH */ +static int is_platform_with_100x_series_pch(void) +{ + if (chipset >= CHIPSET_100_200_SERIES_SUNRISE_POINT && + chipset <= CHIPSET_500_SERIES_TIGER_POINT) + return 1; + + return 0; +} + static void dump_fcba(const fcba_t *fcba) { printf("\nFound Component Section\n"); @@ -560,9 +571,21 @@ (fcba->flill >> 8) & 0xff); printf(" Invalid Instruction 0: 0x%02x\n", fcba->flill & 0xff); - printf("FLPB 0x%08x\n", fcba->flpb); - printf(" Flash Partition Boundary Address: 0x%06x\n\n", - (fcba->flpb & 0xfff) << 12); + if (is_platform_with_100x_series_pch()) { + printf("FLILL1 0x%08x\n", fcba->flpb); + printf(" Invalid Instruction 7: 0x%02x\n", + (fcba->flpb >> 24) & 0xff); + printf(" Invalid Instruction 6: 0x%02x\n", + (fcba->flpb >> 16) & 0xff); + printf(" Invalid Instruction 5: 0x%02x\n", + (fcba->flpb >> 8) & 0xff); + printf(" Invalid Instruction 4: 0x%02x\n", + fcba->flpb & 0xff); + } else { + printf("FLPB 0x%08x\n", fcba->flpb); + printf(" Flash Partition Boundary Address: 0x%06x\n\n", + (fcba->flpb & 0xfff) << 12); + } }
static void dump_fpsba(const fdbar_t *fdb, const fpsba_t *fpsba) @@ -769,20 +792,26 @@ else printf("ICH Revision: %s\n", ich_chipset_names[chipset]); printf("FLMAP0: 0x%08x\n", fdb->flmap0); - printf(" NR: %d\n", (fdb->flmap0 >> 24) & 7); + if (!is_platform_with_100x_series_pch()) + printf(" NR: %d\n", (fdb->flmap0 >> 24) & 7); printf(" FRBA: 0x%x\n", ((fdb->flmap0 >> 16) & 0xff) << 4); printf(" NC: %d\n", ((fdb->flmap0 >> 8) & 3) + 1); printf(" FCBA: 0x%x\n", ((fdb->flmap0) & 0xff) << 4);
printf("FLMAP1: 0x%08x\n", fdb->flmap1); - printf(" ISL: 0x%02x\n", (fdb->flmap1 >> 24) & 0xff); + if (is_platform_with_100x_series_pch()) + printf(" PSL: 0x%02x\n", (fdb->flmap1 >> 24) & 0xff); + else + printf(" ISL: 0x%02x\n", (fdb->flmap1 >> 24) & 0xff); printf(" FPSBA: 0x%x\n", ((fdb->flmap1 >> 16) & 0xff) << 4); printf(" NM: %d\n", (fdb->flmap1 >> 8) & 3); printf(" FMBA: 0x%x\n", ((fdb->flmap1) & 0xff) << 4);
- printf("FLMAP2: 0x%08x\n", fdb->flmap2); - printf(" PSL: 0x%04x\n", (fdb->flmap2 >> 8) & 0xffff); - printf(" FMSBA: 0x%x\n", ((fdb->flmap2) & 0xff) << 4); + if (!is_platform_with_100x_series_pch()) { + printf("FLMAP2: 0x%08x\n", fdb->flmap2); + printf(" PSL: 0x%04x\n", (fdb->flmap2 >> 8) & 0xffff); + printf(" FMSBA: 0x%x\n", ((fdb->flmap2) & 0xff) << 4); + }
char *flumap = find_flumap(image, size); uint32_t flumap1 = *(uint32_t *)flumap;
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44817 )
Change subject: util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44817/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44817/1//COMMIT_MSG@12 PS1, Line 12: nouniformity nonuniformity
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44817 )
Change subject: util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44817/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44817/1//COMMIT_MSG@12 PS1, Line 12: nouniformity
nonuniformity
Ack
Hello build bot (Jenkins), Stefan Reinauer,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44817
to look at the new patch set (#2).
Change subject: util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH ......................................................................
util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH
This patch performs below operations: 1. Remove reserved NR field from Gen 5 onwards SPI programming guide 2. Convert ISL to PSL as applicable for Gen 5 onwards PCH 3. Skip FLMAP2 register dump due to nonuniformity since Gen 5 onwards PCH 4. Dump FLILL1 register as applicable for Gen 5 onwards PCH 5. Remove FLPB register as not applicable since Gen 5 PCH
BUG=b:153888802 TEST=Dump FD for Hatch platform as below
ifdtool -d coreboot.rom
PCH Revision: 300 series Cannon Point/ 400 series Ice Point FLMAP0: 0x00040003 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x45100208 PSL: 0x45 FPSBA: 0x100 NM: 2 FMBA: 0x80
FLILL1 0xc7c4b9b7 Invalid Instruction 7: 0xc7 Invalid Instruction 6: 0xc4 Invalid Instruction 5: 0xb9 Invalid Instruction 4: 0xb7
Signed-off-by: Subrata Banik subrata.banik@intel.com Change-Id: I5141ae5dd174659fde5401fac313a701ae4f8f44 --- M util/ifdtool/ifdtool.c 1 file changed, 37 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/44817/2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44817 )
Change subject: util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44817/2/util/ifdtool/ifdtool.c File util/ifdtool/ifdtool.c:
https://review.coreboot.org/c/coreboot/+/44817/2/util/ifdtool/ifdtool.c@802 PS2, Line 802: if (is_platform_with_100x_series_pch()) : printf(" PSL: 0x%02x\n", (fdb->flmap1 >> 24) & 0xff); : else : printf(" ISL: 0x%02x\n", (fdb->flmap1 >> 24) & 0xff); suggestion: use the `is_platform_with_100x_series_pch()` to just print out "PSL" or "ISL", then print the rest separately
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44817 )
Change subject: util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44817/2/util/ifdtool/ifdtool.c File util/ifdtool/ifdtool.c:
https://review.coreboot.org/c/coreboot/+/44817/2/util/ifdtool/ifdtool.c@802 PS2, Line 802: if (is_platform_with_100x_series_pch()) : printf(" PSL: 0x%02x\n", (fdb->flmap1 >> 24) & 0xff); : else : printf(" ISL: 0x%02x\n", (fdb->flmap1 >> 24) & 0xff);
suggestion: use the `is_platform_with_100x_series_pch()` to just print out "PSL" or "ISL", then prin […]
Ack
Hello build bot (Jenkins), Stefan Reinauer,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44817
to look at the new patch set (#3).
Change subject: util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH ......................................................................
util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH
This patch performs below operations: 1. Remove reserved NR field from Gen 5 onwards SPI programming guide 2. Convert ISL to PSL as applicable for Gen 5 onwards PCH 3. Skip FLMAP2 register dump due to nonuniformity since Gen 5 onwards PCH 4. Dump FLILL1 register as applicable for Gen 5 onwards PCH 5. Remove FLPB register as not applicable since Gen 5 PCH
BUG=b:153888802 TEST=Dump FD for Hatch platform as below
ifdtool -d coreboot.rom
PCH Revision: 300 series Cannon Point/ 400 series Ice Point FLMAP0: 0x00040003 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x45100208 PSL: 0x45 FPSBA: 0x100 NM: 2 FMBA: 0x80
FLILL1 0xc7c4b9b7 Invalid Instruction 7: 0xc7 Invalid Instruction 6: 0xc4 Invalid Instruction 5: 0xb9 Invalid Instruction 4: 0xb7
Signed-off-by: Subrata Banik subrata.banik@intel.com Change-Id: I5141ae5dd174659fde5401fac313a701ae4f8f44 --- M util/ifdtool/ifdtool.c 1 file changed, 35 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/44817/3
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44817 )
Change subject: util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH ......................................................................
Patch Set 3:
@Tim, if you can take a look
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44817 )
Change subject: util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44817 )
Change subject: util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH ......................................................................
util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH
This patch performs below operations: 1. Remove reserved NR field from Gen 5 onwards SPI programming guide 2. Convert ISL to PSL as applicable for Gen 5 onwards PCH 3. Skip FLMAP2 register dump due to nonuniformity since Gen 5 onwards PCH 4. Dump FLILL1 register as applicable for Gen 5 onwards PCH 5. Remove FLPB register as not applicable since Gen 5 PCH
BUG=b:153888802 TEST=Dump FD for Hatch platform as below
ifdtool -d coreboot.rom
PCH Revision: 300 series Cannon Point/ 400 series Ice Point FLMAP0: 0x00040003 FRBA: 0x40 NC: 1 FCBA: 0x30 FLMAP1: 0x45100208 PSL: 0x45 FPSBA: 0x100 NM: 2 FMBA: 0x80
FLILL1 0xc7c4b9b7 Invalid Instruction 7: 0xc7 Invalid Instruction 6: 0xc4 Invalid Instruction 5: 0xb9 Invalid Instruction 4: 0xb7
Signed-off-by: Subrata Banik subrata.banik@intel.com Change-Id: I5141ae5dd174659fde5401fac313a701ae4f8f44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44817 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M util/ifdtool/ifdtool.c 1 file changed, 35 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index fa7817a..93f29d4 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -520,6 +520,17 @@
return 0; } + +/* FLMAP0 register bit 24 onwards are reserved from SPT PCH */ +static int is_platform_with_100x_series_pch(void) +{ + if (chipset >= CHIPSET_100_200_SERIES_SUNRISE_POINT && + chipset <= CHIPSET_500_SERIES_TIGER_POINT) + return 1; + + return 0; +} + static void dump_fcba(const fcba_t *fcba) { printf("\nFound Component Section\n"); @@ -562,9 +573,21 @@ (fcba->flill >> 8) & 0xff); printf(" Invalid Instruction 0: 0x%02x\n", fcba->flill & 0xff); - printf("FLPB 0x%08x\n", fcba->flpb); - printf(" Flash Partition Boundary Address: 0x%06x\n\n", - (fcba->flpb & 0xfff) << 12); + if (is_platform_with_100x_series_pch()) { + printf("FLILL1 0x%08x\n", fcba->flpb); + printf(" Invalid Instruction 7: 0x%02x\n", + (fcba->flpb >> 24) & 0xff); + printf(" Invalid Instruction 6: 0x%02x\n", + (fcba->flpb >> 16) & 0xff); + printf(" Invalid Instruction 5: 0x%02x\n", + (fcba->flpb >> 8) & 0xff); + printf(" Invalid Instruction 4: 0x%02x\n", + fcba->flpb & 0xff); + } else { + printf("FLPB 0x%08x\n", fcba->flpb); + printf(" Flash Partition Boundary Address: 0x%06x\n\n", + (fcba->flpb & 0xfff) << 12); + } }
static void dump_fpsba(const fdbar_t *fdb, const fpsba_t *fpsba) @@ -769,20 +792,24 @@ printf("%s", is_platform_with_pch() ? "PCH" : "ICH"); printf(" Revision: %s\n", ich_chipset_names[chipset]); printf("FLMAP0: 0x%08x\n", fdb->flmap0); - printf(" NR: %d\n", (fdb->flmap0 >> 24) & 7); + if (!is_platform_with_100x_series_pch()) + printf(" NR: %d\n", (fdb->flmap0 >> 24) & 7); printf(" FRBA: 0x%x\n", ((fdb->flmap0 >> 16) & 0xff) << 4); printf(" NC: %d\n", ((fdb->flmap0 >> 8) & 3) + 1); printf(" FCBA: 0x%x\n", ((fdb->flmap0) & 0xff) << 4);
printf("FLMAP1: 0x%08x\n", fdb->flmap1); - printf(" ISL: 0x%02x\n", (fdb->flmap1 >> 24) & 0xff); + printf(" %s: ", is_platform_with_100x_series_pch() ? "PSL" : "ISL"); + printf("0x%02x\n", (fdb->flmap1 >> 24) & 0xff); printf(" FPSBA: 0x%x\n", ((fdb->flmap1 >> 16) & 0xff) << 4); printf(" NM: %d\n", (fdb->flmap1 >> 8) & 3); printf(" FMBA: 0x%x\n", ((fdb->flmap1) & 0xff) << 4);
- printf("FLMAP2: 0x%08x\n", fdb->flmap2); - printf(" PSL: 0x%04x\n", (fdb->flmap2 >> 8) & 0xffff); - printf(" FMSBA: 0x%x\n", ((fdb->flmap2) & 0xff) << 4); + if (!is_platform_with_100x_series_pch()) { + printf("FLMAP2: 0x%08x\n", fdb->flmap2); + printf(" PSL: 0x%04x\n", (fdb->flmap2 >> 8) & 0xffff); + printf(" FMSBA: 0x%x\n", ((fdb->flmap2) & 0xff) << 4); + }
char *flumap = find_flumap(image, size); uint32_t flumap1 = *(uint32_t *)flumap;
-
Patrick Georgi (Code Review) -
Subrata Banik (Code Review)
-
Tim Wawrzynczak (Code Review)