[L] Change in coreboot[main]: soc/intel/ptl: Add GPE1 defines

[Cliff Huang (Code Review)]

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik.

Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email )

Change subject: soc/intel/ptl: Add GPE1 defines
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Patch Set 9:

(1 comment)

File src/soc/intel/pantherlake/include/soc/pm.h:

https://review.coreboot.org/c/coreboot/+/84297/comment/e4a93bcb_3e1f18a6?usp... :
PS9, Line 133: #if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1)
> we can drop this CPP. […]

Subrata, we are still switching in between using GPE0 and GPE1 for further validation until we verify all GPE1 bits are working at this time. here, we will still need this flag here, and also in ASL files and code for SSDT.