Change in coreboot[master]: mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports
V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48619 )
Change subject: mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports ......................................................................
mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports
This change enables PCIEXP_HOTPLUG to support resource allocation for TCSS TBT/USB4 ports.
Change-Id: I5f883dac0d7e5fa84ad2e1683f84c933a90cea51 Signed-off-by: V Sowmya v.sowmya@intel.com --- M src/mainboard/intel/adlrvp/Kconfig 1 file changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/48619/1
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index b6d3ff3..369ce21 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -15,6 +15,7 @@ select SOC_INTEL_ALDERLAKE select HAVE_SPD_IN_CBFS select DRIVERS_SOUNDWIRE_ALC711 + select PCIEXP_HOTPLUG
config CHROMEOS bool @@ -77,6 +78,18 @@ select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC endchoice
+config PCIEXP_HOTPLUG_BUSES + int + default 42 + +config PCIEXP_HOTPLUG_MEM + hex + default 0xc200000 # 194 MiB + +config PCIEXP_HOTPLUG_PREFETCH_MEM + hex + default 0x1c000000 # 448 MiB + config VBOOT select VBOOT_LID_SWITCH select VBOOT_MOCK_SECDATA
V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48619 )
Change subject: mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports ......................................................................
Patch Set 1:
This change is ready for review.
V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48619 )
Change subject: mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports ......................................................................
Patch Set 1:
This change is ready for review.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48619 )
Change subject: mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports ......................................................................
Patch Set 1: Code-Review+2
@sowmya, kindly mention TGL CL as well for reference in commit msg
Hello build bot (Jenkins), Subrata Banik, Meera Ravindranath, Sridhar Siricilla, Balaji Manigandan, Aamir Bohra,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48619
to look at the new patch set (#2).
Change subject: mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports ......................................................................
mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports
This change enables PCIEXP_HOTPLUG to support resource allocation for TCSS TBT/USB4 ports. Referred from TGLRVP -> https://review.coreboot.org/c/coreboot/+/41543
Change-Id: I5f883dac0d7e5fa84ad2e1683f84c933a90cea51 Signed-off-by: V Sowmya v.sowmya@intel.com --- M src/mainboard/intel/adlrvp/Kconfig 1 file changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/48619/2
V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48619 )
Change subject: mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports ......................................................................
Patch Set 2:
Patch Set 1: Code-Review+2
@sowmya, kindly mention TGL CL as well for reference in commit msg
Done
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48619 )
Change subject: mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports ......................................................................
mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports
This change enables PCIEXP_HOTPLUG to support resource allocation for TCSS TBT/USB4 ports. Referred from TGLRVP -> https://review.coreboot.org/c/coreboot/+/41543
Change-Id: I5f883dac0d7e5fa84ad2e1683f84c933a90cea51 Signed-off-by: V Sowmya v.sowmya@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48619 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/Kconfig 1 file changed, 13 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index b6d3ff3..369ce21 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -15,6 +15,7 @@ select SOC_INTEL_ALDERLAKE select HAVE_SPD_IN_CBFS select DRIVERS_SOUNDWIRE_ALC711 + select PCIEXP_HOTPLUG
config CHROMEOS bool @@ -77,6 +78,18 @@ select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC endchoice
+config PCIEXP_HOTPLUG_BUSES + int + default 42 + +config PCIEXP_HOTPLUG_MEM + hex + default 0xc200000 # 194 MiB + +config PCIEXP_HOTPLUG_PREFETCH_MEM + hex + default 0x1c000000 # 448 MiB + config VBOOT select VBOOT_LID_SWITCH select VBOOT_MOCK_SECDATA
-
Hung-Te Lin (Code Review) -
Subrata Banik (Code Review)
-
V Sowmya (Code Review)