Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46428 )
Change subject: soc/intel/skylake/cpu.c: Fix comment coding style ......................................................................
soc/intel/skylake/cpu.c: Fix comment coding style
This comment does not follow any of the styles outlined in the coding style page of the documentation. Adjust it to match the preferred style.
Change-Id: Idf6d0ea69a08e378266b4256c476580889adfca8 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/skylake/cpu.c 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/46428/1
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 79fcda1..f1b40f6 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -34,10 +34,10 @@
if (conf->speed_shift_enable) { /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - is supported or not. coreboot needs to configure MSR 0x1AA - which is then reflected in the CPUID register. - */ + * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP + * is supported or not. coreboot needs to configure MSR 0x1AA + * which is then reflected in the CPUID register. + */ msr = rdmsr(MSR_MISC_PWR_MGMT); msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46428 )
Change subject: soc/intel/skylake/cpu.c: Fix comment coding style ......................................................................
Patch Set 1: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46428 )
Change subject: soc/intel/skylake/cpu.c: Fix comment coding style ......................................................................
Patch Set 1:
Landed early due to simplicity
Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46428 )
Change subject: soc/intel/skylake/cpu.c: Fix comment coding style ......................................................................
soc/intel/skylake/cpu.c: Fix comment coding style
This comment does not follow any of the styles outlined in the coding style page of the documentation. Adjust it to match the preferred style.
Change-Id: Idf6d0ea69a08e378266b4256c476580889adfca8 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46428 Reviewed-by: Michael Niewöhner foss@mniewoehner.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/skylake/cpu.c 1 file changed, 4 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 79fcda1..f1b40f6 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -34,10 +34,10 @@
if (conf->speed_shift_enable) { /* - * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP - is supported or not. coreboot needs to configure MSR 0x1AA - which is then reflected in the CPUID register. - */ + * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP + * is supported or not. coreboot needs to configure MSR 0x1AA + * which is then reflected in the CPUID register. + */ msr = rdmsr(MSR_MISC_PWR_MGMT); msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */
-
Angel Pons (Code Review) -
Michael Niewöhner (Code Review)