[M] Change in coreboot[master]: soc/amd/common/acpi: Implement DTTS Proposal

[Tim Van Patten (Code Review)]

Attention is currently required from: Raul Rangel, Jason Nien, EricKY Cheng, Matt DeVillier, Paul Menzel, Eric Lai, Martin Roth, Eric Peers, LeilaCY Lin, Jason Glenesk, Caveh Jalali, Tim Wawrzynczak, Fred Reitberger, Karthikeyan Ramasubramanian, Boris Mittelberg, Felix Held.

Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68471 )

Change subject: soc/amd/common/acpi: Implement DTTS Proposal
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Patch Set 71:

(1 comment)

File src/soc/amd/common/acpi/dtts.asl:

https://review.coreboot.org/c/coreboot/+/68471/comment/425dff92_505f6137 
PS71, Line 13:         // Set table A as default table after power on device
             :         If (_SB.PRTN == 7)
             :         {
             :             _SB.DDEF()
             :             Store (0, _SB.PRTN)
             :             Return (Zero)
             :         }
> Jut an FYI: The values from the "default" table will be passed into FSP and FSP will perform the ini […]

Adding to this, the FSP update work is being tracked in b/245942343. That bug is currently only for adding the following:

```
vrm_current_limit_mA;
vrm_maximum_current_limit_mA;
vrm_soc_current_limit_mA;
```

I'll point that bug to this CL though, so we can make sure everything is added.