Change in coreboot[master]: vc/mediatek/mt8195: Improve DRAM stability by impedance tracking

[Hung-Te Lin (Code Review)]

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56620 )

Change subject: vc/mediatek/mt8195: Improve DRAM stability by impedance tracking
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vc/mediatek/mt8195: Improve DRAM stability by impedance tracking

Enable the impedance tracking for channel 2 and channel 3.
The impedance tracking can compensate the settings of impedance
when the temperature changes.

Signed-off-by: Ryan Chuang 
Change-Id: I047ab70bb59736a8ba8ae75ab15659900c784342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56620
Reviewed-by: Yu-Ping Wu 
Reviewed-by: Hung-Te Lin 
Tested-by: build bot (Jenkins) 
---
M src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c
1 file changed, 5 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Hung-Te Lin: Looks good to me, but someone else must approve
  Yu-Ping Wu: Looks good to me, approved

diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c
index 187fb0d..f3fc126 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c
@@ -1373,7 +1373,11 @@
    if (channel_num_auxadc > 2) {
     	vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHC_ADDR, P_Fld(0, MISC_IMPCAL_DIS_SUS_CH0_DRV) | P_Fld(1, MISC_IMPCAL_DIS_SUS_CH1_DRV));
        vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHD_ADDR, P_Fld(1, MISC_IMPCAL_DIS_SUS_CH0_DRV) | P_Fld(0, MISC_IMPCAL_DIS_SUS_CH1_DRV));
-		}
+	    vIO32WriteFldMulti(DDRPHY_REG_MISC_CTRL0 + SHIFT_TO_CHC_ADDR, P_Fld(0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT) | P_Fld(0x0, MISC_CTRL0_IMPCAL_TRACK_DISABLE));
+	    vIO32WriteFldMulti(DDRPHY_REG_MISC_CTRL0 + SHIFT_TO_CHD_ADDR, P_Fld(0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT) | P_Fld(0x1, MISC_CTRL0_IMPCAL_TRACK_DISABLE));
+	    vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHC_ADDR, P_Fld(0, MISC_IMPCAL_IMPSRCEXT) | P_Fld(1, MISC_IMPCAL_IMPCAL_ECO_OPT));
+	    vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHD_ADDR, P_Fld(1, MISC_IMPCAL_IMPSRCEXT) | P_Fld(0, MISC_IMPCAL_IMPCAL_ECO_OPT));
+	}
 #endif

//Maoauo: keep following setting for SPMFW enable REFCTRL0_DRVCGWREF = 1 (Imp SW Save mode)