Change in coreboot[master]: mb/google/dedede/var/storo: Update DPTF parameters

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56069 )

Change subject: mb/google/dedede/var/storo: Update DPTF parameters
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mb/google/dedede/var/storo: Update DPTF parameters

Update DPTF parameters from internal thermal team.

BUG=b:180875582
BRANCH=dedede
TEST=emerge-dedede coreboot

Signed-off-by: Tao Xia 
Change-Id: I6d87bc63a66ff38bc2f706d58b8537c052bf4594
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56069
Tested-by: build bot (Jenkins) 
Reviewed-by: Weimin Wu 
Reviewed-by: Karthik Ramasubramanian 
---
M src/mainboard/google/dedede/variants/storo/overridetree.cb
1 file changed, 4 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Karthik Ramasubramanian: Looks good to me, approved
  Weimin Wu: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb
index 7ddadbd..e824652 100644
--- a/src/mainboard/google/dedede/variants/storo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb
@@ -77,16 +77,16 @@
    	.tdp_pl2_override = 20,
    }"

-	register "tcc_offset" = "5"    # TCC of 100C
+	register "tcc_offset" = "10"    # TCC of 95C

device domain 0 on
    	device pci 04.0 on
    		chip drivers/intel/dptf
    			## Passive Policy
    			register "policies.passive" = "{
-					[0] = DPTF_PASSIVE(CPU,     TEMP_SENSOR_1, 60,  3000),
-					[1] = DPTF_PASSIVE(CPU,     TEMP_SENSOR_2, 60,  3000),
-					[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 60,  3000),}"
+					[0] = DPTF_PASSIVE(CPU,     TEMP_SENSOR_1, 67,  3000),
+					[1] = DPTF_PASSIVE(CPU,     TEMP_SENSOR_2, 67,  3000),
+					[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 67,  3000),}"
    			## Critical Policy
    			register "policies.critical" = "{
    				[0] = DPTF_CRITICAL(CPU,          105, SHUTDOWN),