[L] Change in coreboot[main]: [WIP]soc/intel/xeon_sp: Use common _CRS code generation

[Patrick Rudolph (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu.

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80796?usp=email )

Change subject: [WIP]soc/intel/xeon_sp: Use common _CRS code generation
......................................................................

Patch Set 3:

(1 comment)

File src/soc/intel/xeon_sp/spr/soc_acpi.c:

https://review.coreboot.org/c/coreboot/+/80796/comment/bcf0db4a_318126cd :
PS3, Line 78: /* For stack with CXL device, the PCIe bus resource is BusBase only. */
            : 		if (is_iio_cxl_stack_res(ri))
            : 			acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusBase, 0x0, 1);
> I had a very similar patchtrain to this one. CXL stacks are a problem... […]

Yes, that's what the reference code does.
The CXL domain starts at ri->BusBase+1, but the PCI domain covers all PCI buses.