Change in coreboot[master]: soc/intel/cannonlake: Add options for pcie ltr

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/29642

Change subject: soc/intel/cannonlake: Add options for pcie ltr
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soc/intel/cannonlake: Add options for pcie ltr

FSP can support enable/disable Pci express LTR (Latency Tolerance
Reporting) mechansism through upd interface. Include that into coreboot
side.

BUG=N/A
TEST=N/A

Change-Id: I69b423afa4f81a2d58375734bba07792e08931d5
Signed-off-by: Lijian Zhao 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/29642/1

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 015133e..b976cd2 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -165,6 +165,8 @@
    /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
     * clksrc. */
    uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS];
+	/* PCIe LTR(Latency Tolerance Reporting) mechanism */
+	uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];

/* eMMC and SD */
    uint8_t ScsEmmcHs400Enabled;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 3314f6d..f957459 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -171,6 +171,8 @@
           sizeof(config->PcieClkSrcUsage));
    memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
           sizeof(config->PcieClkSrcClkReq));
+	memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
+	       sizeof(config->PcieRpLtrEnable));

/* eMMC and SD */
    dev = dev_find_slot(0, PCH_DEVFN_EMMC);