[M] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu.

Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81374?usp=email )

Change subject: soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt
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Patch Set 16:

(1 comment)

File src/soc/intel/xeon_sp/gnr/soc_acpi.c:

https://review.coreboot.org/c/coreboot/+/81374/comment/5b2c4732_7a1cfc13 :
PS16, Line 85: 		acpigen_emit_eisaid("ACPI0016");
updated to ACPI0016 per CXL spec 3.1

9.18.2 CXL _OSC
According to ACPI Specification, _OSC (Operating System Capabilities) is a control
method that is used by OSs to communicate to the System Firmware the capabilities
supported by the OS and to negotiate ownership of specific capabilities.
The _OSC interface defined in this section applies only to “Host Bridge” ACPI devices
that originate CXL hierarchies. As specified in Section 9.12, these ACPI devices must
have an _HID of (or a _CID that includes) EISAID(“ACPI0016”). CXL _OSC is required
for a CXL VH. CXL _OSC is optional for an RCD. A CXL Host Bridge also originates a
PCIe hierarchy and will have a _CID of EISAID(“PNP0A08”). As such, a CXL Host Bridge
device may expose both CXL _OSC and PCIe _OSC.
The _OSC interface for a CXL Host Bridge is identified by the Universal Unique Identifier
(UUID) 68f2d50b-c469-4d8a-bd3d-941a103fd3fc.