Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31368
Change subject: [WIP]mb/google: Remove TOL_1V8 setting for pads in GPP_F ......................................................................
[WIP]mb/google: Remove TOL_1V8 setting for pads in GPP_F
Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c Signed-off-by: Kane Chen kane.chen@intel.com --- M src/mainboard/google/fizz/variants/baseboard/gpio.c M src/mainboard/google/poppy/variants/baseboard/gpio.c M src/mainboard/google/poppy/variants/nami/gpio.c M src/mainboard/google/poppy/variants/nautilus/gpio.c M src/mainboard/google/poppy/variants/soraka/gpio.c 5 files changed, 26 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/31368/1
diff --git a/src/mainboard/google/fizz/variants/baseboard/gpio.c b/src/mainboard/google/fizz/variants/baseboard/gpio.c index 4cd3865..7ea5c6f 100644 --- a/src/mainboard/google/fizz/variants/baseboard/gpio.c +++ b/src/mainboard/google/fizz/variants/baseboard/gpio.c @@ -193,9 +193,9 @@ /* I2C3_SCL */ PAD_CFG_NC(GPP_F7), /* I2C4_SDA */ PAD_CFG_NC(GPP_F8), /* I2C4_SCL */ PAD_CFG_NC(GPP_F9), -/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, +/* I2C5_SDA */ PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SDA */ -/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, +/* I2C5_SCL */ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), /* PCH_I2C2_AUDIO_1V8_SCL */ /* EMMC_CMD */ PAD_CFG_NC(GPP_F12), /* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index c731b52..c007b7f 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -268,21 +268,21 @@ /* F3 : I2S2_RXD ==> NC */ PAD_CFG_NC(GPP_F3), /* F4 : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */ - PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */ - PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* F6 : I2C3_SDA ==> PCH_I2C3_PEN_1V8_SDA */ - PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* F7 : I2C3_SCL ==> PCH_I2C3_PEN_1V8_SCL */ - PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* F8 : I2C4_SDA ==> PCH_I2C4_UFCAM_1V8_SDA */ - PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* F9 : I2C4_SCL ==> PCH_I2C4_UFCAM_1V8_SCL */ - PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* F10 : I2C5_SDA ==> PCH_I2C5_AUDIO_1V8_SDA */ - PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), /* F11 : I2C5_SCL ==> PCH_I2C5_AUDIO_1V8_SCL */ - PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), /* F12 : EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* F13 : EMMC_DATA0 */ diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index cd7e0ca..6d45c73 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -265,13 +265,13 @@ /* F3 : I2S2_RXD ==> NC */ PAD_CFG_NC(GPP_F3), /* F4 : I2C2_SDA ==> I2C_2_SDA */ - PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> I2C_2_SCL */ - PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* F6 : I2C3_SDA ==> I2C_3_SDA */ - PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* F7 : I2C3_SCL ==> I2C_3_SCL */ - PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* F8 : I2C4_SDA ==> I2C_4_SDA (unstuffed) */ PAD_CFG_NC(GPP_F8), /* F9 : I2C4_SCL ==> I2C_4_SCL (unstuffed) */ diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c index 4f80e2f..9fa8748 100644 --- a/src/mainboard/google/poppy/variants/nautilus/gpio.c +++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c @@ -259,13 +259,13 @@ /* F3 : I2S2_RXD ==> NC */ PAD_CFG_NC(GPP_F3), /* F4 : I2C2_SDA ==> CHP1_I2C2_CAM_PMIC_SDA */ - PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> CHP1_I2C2_CAM_PMIC_SCL */ - PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* F6 : I2C3_SDA ==> CHP1_I2C3_DIG_SDA */ - PAD_CFG_NF_1V8(GPP_F6, 5K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_F6, 5K_PU, DEEP, NF1), /* F7 : I2C3_SCL ==> CHP1_I2C3_DIG_SCL */ - PAD_CFG_NF_1V8(GPP_F7, 5K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_F7, 5K_PU, DEEP, NF1), /* F8 : I2C4_SDA ==> CHP1_I2C4_TP_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* F9 : I2C4_SCL ==> CHP1_I2C4_TP_SCL */ diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c index 0e24bb7..25240f0 100644 --- a/src/mainboard/google/poppy/variants/soraka/gpio.c +++ b/src/mainboard/google/poppy/variants/soraka/gpio.c @@ -268,21 +268,21 @@ /* F3 : I2S2_RXD ==> NC */ PAD_CFG_NC(GPP_F3), /* F4 : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */ - PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* F5 : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */ - PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* F6 : I2C3_SDA ==> PCH_I2C3_PEN_1V8_SDA */ - PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* F7 : I2C3_SCL ==> PCH_I2C3_PEN_1V8_SCL */ - PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* F8 : I2C4_SDA ==> PCH_I2C4_UFCAM_1V8_SDA */ - PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* F9 : I2C4_SCL ==> PCH_I2C4_UFCAM_1V8_SCL */ - PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* F10 : I2C5_SDA ==> PCH_I2C5_AUDIO_1V8_SDA */ - PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), /* F11 : I2C5_SCL ==> PCH_I2C5_AUDIO_1V8_SCL */ - PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), /* F12 : EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* F13 : EMMC_DATA0 */
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31368 )
Change subject: [WIP]mb/google: Remove TOL_1V8 setting for pads in GPP_F ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/31368/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31368/1//COMMIT_MSG@8 PS1, Line 8: Why?
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31368
to look at the new patch set (#2).
Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11 ......................................................................
soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11
According to doc 609208, bit 25 TOL_1V8 in GPP_F4 ~ GPP_F11 DW1 should be clear to prevent unexpected I2C behaviors.
BUG=b:124269499 TEST=boot on nami and check bit 25 TOL_1V8 is clear
Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c Signed-off-by: Kane Chen kane.chen@intel.com --- M src/soc/intel/common/block/gpio/gpio.c 1 file changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/31368/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31368 )
Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11 ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31368/2/src/soc/intel/common/block/gpio/gpio... File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/#/c/31368/2/src/soc/intel/common/block/gpio/gpio... PS2, Line 282: if (cfg->pad >= GPP_F4 && cfg->pad suspect code indent for conditional statements (16, 23)
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31368
to look at the new patch set (#3).
Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11 ......................................................................
soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11
According to doc 609208, bit 25 TOL_1V8 in GPP_F4 ~ GPP_F11 DW1 should be clear to prevent unexpected I2C behaviors.
BUG=b:124269499 TEST=boot on nami and check bit 25 TOL_1V8 is clear
Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c Signed-off-by: Kane Chen kane.chen@intel.com --- M src/soc/intel/common/block/gpio/gpio.c 1 file changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/31368/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31368 )
Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11 ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/31368/3/src/soc/intel/common/block/gpio/gpio... File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/#/c/31368/3/src/soc/intel/common/block/gpio/gpio... PS3, Line 282: if (cfg->pad >= GPP_F4 && cfg->pad <= GPP_F11 suspect code indent for conditional statements (16, 23)
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31368
to look at the new patch set (#4).
Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11 ......................................................................
soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11
According to doc 609208, bit 25 TOL_1V8 in GPP_F4 ~ GPP_F11 DW1 should be clear to prevent unexpected I2C behaviors.
BUG=b:124269499 TEST=boot on nami and check bit 25 TOL_1V8 is clear
Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c Signed-off-by: Kane Chen kane.chen@intel.com --- M src/soc/intel/common/block/gpio/gpio.c 1 file changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/31368/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31368 )
Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11 ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/31368/4/src/soc/intel/common/block/gpio/gpio... File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/#/c/31368/4/src/soc/intel/common/block/gpio/gpio... PS4, Line 282: if (cfg->pad >= GPP_F4 && cfg->pad <= GPP_F11 suspect code indent for conditional statements (16, 23)
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31368
to look at the new patch set (#5).
Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11 ......................................................................
soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11
According to doc 609208, bit 25 TOL_1V8 in GPP_F4 ~ GPP_F11 DW1 should be clear to prevent unexpected I2C behaviors.
BUG=b:124269499 TEST=boot on nami and check bit 25 TOL_1V8 is clear
Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c Signed-off-by: Kane Chen kane.chen@intel.com --- M src/soc/intel/common/block/gpio/gpio.c 1 file changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/31368/5
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31368 )
Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11 ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/#/c/31368/5/src/soc/intel/common/block/gpio/gpio... File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/#/c/31368/5/src/soc/intel/common/block/gpio/gpio... PS5, Line 280: * ~ GPP_F11. code indent should use tabs where possible
https://review.coreboot.org/#/c/31368/5/src/soc/intel/common/block/gpio/gpio... PS5, Line 282: if (cfg->pad >= GPP_F4 && cfg->pad <= GPP_F11 && suspect code indent for conditional statements (16, 23)
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31368
to look at the new patch set (#6).
Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11 ......................................................................
soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11
According to doc 609208, bit 25 TOL_1V8 in GPP_F4 ~ GPP_F11 DW1 should be clear to prevent unexpected I2C behaviors.
BUG=b:124269499 TEST=boot on nami and check bit 25 TOL_1V8 is clear
Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c Signed-off-by: Kane Chen kane.chen@intel.com --- M src/soc/intel/common/block/gpio/gpio.c 1 file changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/31368/6
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31368 )
Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11 ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/31368/6/src/soc/intel/common/block/gpio/gpio... File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/#/c/31368/6/src/soc/intel/common/block/gpio/gpio... PS6, Line 282: if (cfg->pad >= GPP_F4 && cfg->pad <= GPP_F11 && suspect code indent for conditional statements (16, 23)
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31368 )
Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11 ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/31368/6/src/soc/intel/common/block/gpio/gpio... File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/#/c/31368/6/src/soc/intel/common/block/gpio/gpio... PS6, Line 276: #if IS_ENABLED(CONFIG_SOC_INTEL_SKYLAKE) && \ are the preprocessor checks required ?
Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31368 )
Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11 ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/31368/6/src/soc/intel/common/block/gpio/gpio... File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/#/c/31368/6/src/soc/intel/common/block/gpio/gpio... PS6, Line 276: #if IS_ENABLED(CONFIG_SOC_INTEL_SKYLAKE) && \
are the preprocessor checks required ?
This common gpio code will be used for other chipset as well, so I add a preprocessor here. Thanks
Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31368 )
Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11 ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/31368/6/src/soc/intel/common/block/gpio/gpio... File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/#/c/31368/6/src/soc/intel/common/block/gpio/gpio... PS6, Line 282: if (cfg->pad >= GPP_F4 && cfg->pad <= GPP_F11 &&
suspect code indent for conditional statements (16, 23)
i actually can't understand what build bod mean. this line should be indented properly
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31368 )
Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11 ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/31368/6/src/soc/intel/common/block/gpio/gpio... File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/#/c/31368/6/src/soc/intel/common/block/gpio/gpio... PS6, Line 286: } Can we add an soc callback that returns the pad conf?
uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, int dw_reg, uint32_t reg)
default weak implementation would be:
uint32_t __weak soc_gpio_pad_config_fixup(const struct pad_config *cfg, int dw_reg, uint32_t reg) { return reg; }
Then SoC specific implementation can do its own fixups internally instead of littering the common code.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31368 )
Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11 ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/31368/6/src/soc/intel/common/block/gpio/gpio... File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/#/c/31368/6/src/soc/intel/common/block/gpio/gpio... PS6, Line 286: }
Can we add an soc callback that returns the pad conf? […]
+1
Hello Aaron Durbin, Patrick Rudolph, Subrata Banik, Duncan Laurie, Gaggery Tsai, Marx Wang, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31368
to look at the new patch set (#7).
Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11 ......................................................................
soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11
According to doc 609208, bit 25 TOL_1V8 in GPP_F4 ~ GPP_F11 DW1 should be clear to prevent unexpected I2C behaviors.
BUG=b:124269499 TEST=boot on nami and check bit 25 TOL_1V8 is clear
Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c Signed-off-by: Kane Chen kane.chen@intel.com --- M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/skylake/gpio.c 3 files changed, 28 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/31368/7
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31368 )
Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11 ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/#/c/31368/7/src/soc/intel/common/block/include/i... File src/soc/intel/common/block/include/intelblocks/gpio.h:
https://review.coreboot.org/#/c/31368/7/src/soc/intel/common/block/include/i... PS7, Line 202: reg Maybe reg_val? Just to make it clear that this is the register value. Can you please add a comment indicating what each param indicates?
https://review.coreboot.org/#/c/31368/7/src/soc/intel/skylake/gpio.c File src/soc/intel/skylake/gpio.c:
https://review.coreboot.org/#/c/31368/7/src/soc/intel/skylake/gpio.c@175 PS7, Line 175: #if !IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H) : /* Just use: if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)) return;
...
Hello Aaron Durbin, Patrick Rudolph, Subrata Banik, Duncan Laurie, Gaggery Tsai, Marx Wang, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31368
to look at the new patch set (#8).
Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11 ......................................................................
soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11
According to doc 609208, bit 25 TOL_1V8 in GPP_F4 ~ GPP_F11 DW1 should be clear to prevent unexpected I2C behaviors.
BUG=b:124269499 TEST=boot on nami and check bit 25 TOL_1V8 is clear
Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c Signed-off-by: Kane Chen kane.chen@intel.com --- M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/skylake/gpio.c 3 files changed, 34 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/31368/8
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31368 )
Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11 ......................................................................
Patch Set 8: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31368 )
Change subject: soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11 ......................................................................
soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11
According to doc 609208, bit 25 TOL_1V8 in GPP_F4 ~ GPP_F11 DW1 should be clear to prevent unexpected I2C behaviors.
BUG=b:124269499 TEST=boot on nami and check bit 25 TOL_1V8 is clear
Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c Signed-off-by: Kane Chen kane.chen@intel.com Reviewed-on: https://review.coreboot.org/c/31368 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/skylake/gpio.c 3 files changed, 34 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 6390315..d77e052 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -273,6 +273,9 @@ soc_pad_conf &= mask[i]; soc_pad_conf |= pad_conf & ~mask[i];
+ /* Patch GPIO settings for SoC specifically */ + soc_pad_conf = soc_gpio_pad_config_fixup(cfg, i, soc_pad_conf); + if (IS_ENABLED(CONFIG_DEBUG_GPIO)) printk(BIOS_DEBUG, "gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x" @@ -571,3 +574,9 @@ const struct pad_community *comm = gpio_get_community(gpio_num); return comm->acpi_path; } + +uint32_t __weak soc_gpio_pad_config_fixup(const struct pad_config *cfg, + int dw_reg, uint32_t reg_val) +{ + return reg_val; +} diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index c389ec4..11a03d0 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -197,5 +197,15 @@ */ uint8_t gpio_get_pad_portid(const gpio_t pad);
+/* + * Function to patch GPIO settings for SoC specifically + * cfg = pad config contains pad number and reg value. + * dw_reg = pad config dword number. + * reg_val = the reg value need to be patched. + * Returns gpio setting patched for SoC specifically + */ +uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, + int dw_reg, uint32_t reg_val); + #endif #endif /* _SOC_INTELBLOCKS_GPIO_H_ */ diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index f67d4a3..4da705d 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -168,3 +168,18 @@ *num = ARRAY_SIZE(routes); return routes; } + +uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, + int dw_reg, uint32_t reg_val) +{ + if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)) + return reg_val; + /* + * For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4 + * ~ GPP_F11. + */ + if (cfg->pad >= GPP_F4 && cfg->pad <= GPP_F11 && dw_reg == 1) + reg_val = reg_val & ~(PAD_CFG1_TOL_1V8); + return reg_val; + +}
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Aaron Durbin (Code Review) -
build bot (Jenkins) (Code Review)
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Furquan Shaikh (Code Review)
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Kane Chen (Code Review)
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Patrick Georgi (Code Review)
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Patrick Rudolph (Code Review)
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Paul Menzel (Code Review)