HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31254
Change subject: mainboard/(i82801gx): Move early_ich7_init() to southbridge ......................................................................
mainboard/(i82801gx): Move early_ich7_init() to southbridge
Change-Id: Idab66c675b5bcb068a720a66e722b1d8275c19bb Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/southbridge/intel/i82801gx/Makefile.inc M src/southbridge/intel/i82801gx/i82801gx.h 13 files changed, 8 insertions(+), 531 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/31254/1
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index ad184a8..394b486 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -175,59 +175,6 @@ RCBA32(0x1e98) = 0x000c0801; }
-static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - /* program secondary mlt XXX byte? */ - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - - /* reset rtc power status */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - - /* usb transient disconnect */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - /* next step only on ich7m b0 and later: */ - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; -} - void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index ba50471..e70f119 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -123,59 +123,6 @@ RCBA32(CG) = 0x00000001; }
-static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - - // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - - // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030509; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; -} - void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0, boot_mode = 0; diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 471977f..d316fbd 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -179,59 +179,6 @@ RCBA32(0x1e98) = 0x000c0801; }
-static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - - // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - - // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(0x3410); - reg32 |= (1 << 6); - RCBA32(0x3410) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; -} - void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index 55b1549..51bf1d8 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -86,59 +86,6 @@ RCBA32(CG) = 0x00000001; }
-static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - - // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - - // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030509; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; -} - void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0, boot_mode = 0; diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 9eaa8de..c4a2370 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -145,59 +145,6 @@ // RCBA32(0x341c) = 0x00000001; }
-static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - - // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - - // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; -} - void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 1019805..fbfcc0f 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -44,6 +44,12 @@ default "Intel_whlrvp" if BOARD_INTEL_WHISKEYLAKE_RVP default "Intel_cflrvp"
+config CHROMEOS + bool + default n if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 + default y + select GBB_FLAG_FORCE_MANUAL_RECOVERY + config MAX_CPUS int default 12 if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 5e3535a..56c205c 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -67,59 +67,6 @@ // RCBA32(0x341c) = 0x00000001; }
-static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - - // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - - // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(0x3410); - reg32 |= (1 << 6); - RCBA32(0x3410) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; -} - void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0, boot_mode = 0; diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index fda8f97..01ccaa7 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -186,59 +186,6 @@
}
-static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - /* program secondary mlt XXX byte? */ - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - - /* reset rtc power status */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - - /* usb transient disconnect */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - /* next step only on ich7m b0 and later: */ - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; -} - void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 6f66c88..e568594 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -105,59 +105,6 @@ RCBA64(IOTR3) = 0x000200f0000c0801ULL; }
-static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - - // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - - // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; -} - void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 6eceaeb..21ffcd5 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -106,59 +106,6 @@ RCBA64(IOTR3) = 0x000200f0000c0801ULL; }
-static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - - // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - - // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; -} - void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 0003401..61a08f6 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -145,59 +145,6 @@ RCBA32(0x1e98) = 0x000c0801; }
-static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - /* program secondary mlt XXX byte? */ - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - - /* reset rtc power status */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - - /* usb transient disconnect */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - /* next step only on ich7m b0 and later: */ - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; -} - static void init_artec_dongle(void) { /* Enable 4MB decoding */ diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 290794b..54a36ab 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -34,6 +34,6 @@
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-romstage-y += early_smbus.c early_lpc.c +romstage-y += early_smbus.c early_lpc.c early_init.c
endif diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 12935c2..c2cef91 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -51,6 +51,7 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); int southbridge_detect_s3_resume(void); +void early_ich7_init(void); #endif #endif
Hello Alexander Couzens, Patrick Rudolph, Arthur Heymans, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31254
to look at the new patch set (#2).
Change subject: mainboard/(i82801gx): Move early_ich7_init() to southbridge ......................................................................
mainboard/(i82801gx): Move early_ich7_init() to southbridge
Change-Id: Idab66c675b5bcb068a720a66e722b1d8275c19bb Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/southbridge/intel/i82801gx/Makefile.inc A src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801gx/i82801gx.h 14 files changed, 81 insertions(+), 531 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/31254/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31254 )
Change subject: mainboard/(i82801gx): Move early_ich7_init() to southbridge ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
I like the idea
https://review.coreboot.org/#/c/31254/2/src/mainboard/intel/coffeelake_rvp/K... File src/mainboard/intel/coffeelake_rvp/Kconfig:
https://review.coreboot.org/#/c/31254/2/src/mainboard/intel/coffeelake_rvp/K... PS2, Line 47: config CHROMEOS : bool : default n if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 : default y : select GBB_FLAG_FORCE_MANUAL_RECOVERY Um?
Hello Alexander Couzens, Patrick Rudolph, Angel Pons, Arthur Heymans, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31254
to look at the new patch set (#3).
Change subject: mainboard/(i82801gx): Move early_ich7_init() to southbridge ......................................................................
mainboard/(i82801gx): Move early_ich7_init() to southbridge
Change-Id: Idab66c675b5bcb068a720a66e722b1d8275c19bb Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/southbridge/intel/i82801gx/Makefile.inc A src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801gx/i82801gx.h 15 files changed, 81 insertions(+), 584 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/31254/3
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31254 )
Change subject: mainboard/(i82801gx): Move early_ich7_init() to southbridge ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31254/2/src/mainboard/intel/coffeelake_rvp/K... File src/mainboard/intel/coffeelake_rvp/Kconfig:
https://review.coreboot.org/#/c/31254/2/src/mainboard/intel/coffeelake_rvp/K... PS2, Line 47: config CHROMEOS : bool : default n if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 : default y : select GBB_FLAG_FORCE_MANUAL_RECOVERY
Um?
"Um" ... also lol
Hello Alexander Couzens, Patrick Rudolph, Angel Pons, Arthur Heymans, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31254
to look at the new patch set (#4).
Change subject: mainboard/(i82801gx): Move early_ich7_init() to southbridge ......................................................................
mainboard/(i82801gx): Move early_ich7_init() to southbridge
Change-Id: Idab66c675b5bcb068a720a66e722b1d8275c19bb Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/southbridge/intel/i82801gx/Makefile.inc A src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801gx/i82801gx.h 14 files changed, 75 insertions(+), 584 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/31254/4
Hello Alexander Couzens, Patrick Rudolph, Angel Pons, Arthur Heymans, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31254
to look at the new patch set (#5).
Change subject: mainboard/(i82801gx): Move early_ich7_init() to southbridge ......................................................................
mainboard/(i82801gx): Move early_ich7_init() to southbridge
Change-Id: Idab66c675b5bcb068a720a66e722b1d8275c19bb Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/southbridge/intel/i82801gx/Makefile.inc A src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801gx/i82801gx.h 14 files changed, 75 insertions(+), 584 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/31254/5
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31254 )
Change subject: mainboard/(i82801gx): Move early_ich7_init() to southbridge ......................................................................
Patch Set 5:
Please split the UL change out into a separate commit, or at least comment about the change in the commit message.
Please also add, how you tested this.
Hello Alexander Couzens, Patrick Rudolph, Angel Pons, Arthur Heymans, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31254
to look at the new patch set (#6).
Change subject: mainboard/(i82801gx): Move early_ich7_init() to southbridge ......................................................................
mainboard/(i82801gx): Move early_ich7_init() to southbridge
Tested on 945G-M4 board.
Change-Id: Idab66c675b5bcb068a720a66e722b1d8275c19bb Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/southbridge/intel/i82801gx/Makefile.inc A src/southbridge/intel/i82801gx/early_init.c M src/southbridge/intel/i82801gx/i82801gx.h 14 files changed, 75 insertions(+), 584 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/31254/6
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31254 )
Change subject: mainboard/(i82801gx): Move early_ich7_init() to southbridge ......................................................................
Patch Set 6: Code-Review+1
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31254 )
Change subject: mainboard/(i82801gx): Move early_ich7_init() to southbridge ......................................................................
Patch Set 6:
(2 comments)
I'm not sure what RCBA32(0x0214) is for, but as far as I've seen this patch changes what's written to that register. Haven't looked too closely into this patch, so there might be other differences I haven't spotted.
https://review.coreboot.org/#/c/31254/6/src/mainboard/asus/p5gc-mx/romstage.... File src/mainboard/asus/p5gc-mx/romstage.c:
https://review.coreboot.org/#/c/31254/6/src/mainboard/asus/p5gc-mx/romstage.... PS6, Line 155: this value is different
https://review.coreboot.org/#/c/31254/6/src/mainboard/gigabyte/ga-945gcm-s2l... File src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c:
https://review.coreboot.org/#/c/31254/6/src/mainboard/gigabyte/ga-945gcm-s2l... PS6, Line 118: this value is different
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31254 )
Change subject: mainboard/(i82801gx): Move early_ich7_init() to southbridge ......................................................................
Patch Set 6: Code-Review-1
(1 comment)
https://review.coreboot.org/#/c/31254/6/src/southbridge/intel/i82801gx/early... File src/southbridge/intel/i82801gx/early_init.c:
https://review.coreboot.org/#/c/31254/6/src/southbridge/intel/i82801gx/early... PS6, Line 51: 10030549 you are right. for the board I have, vendor (and intel) set RCBA32(0x0214)= 0x10030509
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31254 )
Change subject: mainboard/(i82801gx): Move early_ich7_init() to southbridge ......................................................................
Patch Set 6:
looks like this value is RO ... I've set it by mistake to 0x10030549 https://review.coreboot.org/#/c/coreboot/+/25509/25/src/mainboard/nec/945g-m...
and using inteltool on that rom, I got 0x10030509.
so it needs more investigation and test on other boards ...
HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31254 )
Change subject: mainboard/(i82801gx): Move early_ich7_init() to southbridge ......................................................................
Abandoned