Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46053 )
Change subject: soc/intel/alderlake/ramstage: Fix compilation issue ......................................................................
soc/intel/alderlake/ramstage: Fix compilation issue
Refer to commit 0359d9d (soc/intel: Make use of PMC low power program from common block) commit 1366e44 (soc/intel: Move pch_enable_ioapic() to common code) commit 78463a7 (soc/intel: Move soc_pch_pirq_init() to common code) commit 8971ccd (soc/intel: Move pch_misc_init() to common code) for details
Change-Id: Ic83d332cf2bfe8eded1667dd1503e718d854f10b Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/alderlake/espi.c M src/soc/intel/alderlake/include/soc/pmc.h 2 files changed, 4 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/46053/1
diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c index 8a4007c..c909030 100644 --- a/src/soc/intel/alderlake/espi.c +++ b/src/soc/intel/alderlake/espi.c @@ -59,7 +59,7 @@ { /* Legacy initialization */ isa_dma_init(); - lpc_pch_misc_init(); + pch_misc_init();
/* Enable CLKRUN_EN for power gating ESPI */ lpc_enable_pci_clk_cntl(); @@ -71,8 +71,8 @@ lpc_set_serirq_mode(SERIRQ_QUIET);
/* Interrupt configuration */ - lpc_pch_enable_ioapic(); - lpc_pch_pirq_init(); + pch_enable_ioapic(); + pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); } diff --git a/src/soc/intel/alderlake/include/soc/pmc.h b/src/soc/intel/alderlake/include/soc/pmc.h index e4e3dfb..8887d9b 100644 --- a/src/soc/intel/alderlake/include/soc/pmc.h +++ b/src/soc/intel/alderlake/include/soc/pmc.h @@ -125,6 +125,7 @@ enum pch_pmc_xtal pmc_get_xtal_freq(void);
#define PCH_PWRM_ACPI_TMR_CTL 0x18FC +#define ACPI_TIM_DIS (1 << 1) #define GPIO_GPE_CFG 0x1920 #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x))
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46053 )
Change subject: soc/intel/alderlake/ramstage: Fix compilation issue ......................................................................
Patch Set 1:
HI Angel, Tim,
Please consider my apology that I've missed rebasing ADL ramstage CL based on common code CLs hence it results into compilation issue.
Submitting this now. As we have mainboard code ready, hopefully won't rerepeat such mistake for ADL SoC.
Thanks, Subrata
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46053 )
Change subject: soc/intel/alderlake/ramstage: Fix compilation issue ......................................................................
Patch Set 1: Code-Review+2
Patch Set 1:
HI Angel, Tim,
Please consider my apology that I've missed rebasing ADL ramstage CL based on common code CLs hence it results into compilation issue.
Submitting this now. As we have mainboard code ready, hopefully won't rerepeat such mistake for ADL SoC.
Thanks, Subrata
No problem. See, having the code build-tested from the very start is very useful 😄
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46053 )
Change subject: soc/intel/alderlake/ramstage: Fix compilation issue ......................................................................
Patch Set 1:
Patch Set 1: Code-Review+2
Patch Set 1:
HI Angel, Tim,
Please consider my apology that I've missed rebasing ADL ramstage CL based on common code CLs hence it results into compilation issue.
Submitting this now. As we have mainboard code ready, hopefully won't rerepeat such mistake for ADL SoC.
Thanks, Subrata
No problem. See, having the code build-tested from the very start is very useful 😄
agree Angel. i had that plan from beginning but somehow this timeline forced me to go with SOC first model but i will make sure from next SoC onwards we are going with incremental SoC + MB CL from day 1.
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46053 )
Change subject: soc/intel/alderlake/ramstage: Fix compilation issue ......................................................................
soc/intel/alderlake/ramstage: Fix compilation issue
Refer to commit 0359d9d (soc/intel: Make use of PMC low power program from common block) commit 1366e44 (soc/intel: Move pch_enable_ioapic() to common code) commit 78463a7 (soc/intel: Move soc_pch_pirq_init() to common code) commit 8971ccd (soc/intel: Move pch_misc_init() to common code) for details
Change-Id: Ic83d332cf2bfe8eded1667dd1503e718d854f10b Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46053 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/alderlake/espi.c M src/soc/intel/alderlake/include/soc/pmc.h 2 files changed, 4 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c index 8a4007c..c909030 100644 --- a/src/soc/intel/alderlake/espi.c +++ b/src/soc/intel/alderlake/espi.c @@ -59,7 +59,7 @@ { /* Legacy initialization */ isa_dma_init(); - lpc_pch_misc_init(); + pch_misc_init();
/* Enable CLKRUN_EN for power gating ESPI */ lpc_enable_pci_clk_cntl(); @@ -71,8 +71,8 @@ lpc_set_serirq_mode(SERIRQ_QUIET);
/* Interrupt configuration */ - lpc_pch_enable_ioapic(); - lpc_pch_pirq_init(); + pch_enable_ioapic(); + pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); } diff --git a/src/soc/intel/alderlake/include/soc/pmc.h b/src/soc/intel/alderlake/include/soc/pmc.h index e4e3dfb..8887d9b 100644 --- a/src/soc/intel/alderlake/include/soc/pmc.h +++ b/src/soc/intel/alderlake/include/soc/pmc.h @@ -125,6 +125,7 @@ enum pch_pmc_xtal pmc_get_xtal_freq(void);
#define PCH_PWRM_ACPI_TMR_CTL 0x18FC +#define ACPI_TIM_DIS (1 << 1) #define GPIO_GPE_CFG 0x1920 #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x))
-
Angel Pons (Code Review) -
Subrata Banik (Code Review)