New patch to review for coreboot: nb/amd/mct_ddr3: Reenable sync flood after ECC init

[Timothy Pearson]

Timothy Pearson ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14270

-gerrit

commit 6d97336d1897ea2ecf341359d80fc6baf310bdb2
Author: Timothy Pearson 
Date:   Wed Apr 6 22:07:58 2016 -0500

nb/amd/mct_ddr3: Reenable sync flood after ECC init

The sync flood reset fix in Change-Id: I62d897010a8120aa14b4cb8d096bc4f2edc5f248
    and related changes have made it possible to move the sync flood enable statements
    back into romstage.

Change-Id: I5a3a4f1621e3048f9dfc159709410be9de6ebece
    Signed-off-by: Timothy Pearson 
---
 src/northbridge/amd/amdfam10/misc_control.c    | 8 --------
 src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 9 +++++++++
 2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c
index eee5c46..775af66 100644
--- a/src/northbridge/amd/amdfam10/misc_control.c
+++ b/src/northbridge/amd/amdfam10/misc_control.c
@@ -186,14 +186,6 @@ static void misc_control_init(struct device *dev)
    		/* Clear MC4 error status */
    		pci_write_config32(dev, 0x48, 0x0);
    		pci_write_config32(dev, 0x4c, 0x0);
-
-			if (mem_info->dct_stat[node].mca_config_backed_up) {
-				dword = pci_read_config32(dev, 0x44);
-				dword |= (mem_info->dct_stat[node].sync_flood_on_dram_err & 0x1) << 30;
-				dword |= (mem_info->dct_stat[node].sync_flood_on_any_uc_err & 0x1) << 21;
-				dword |= (mem_info->dct_stat[node].sync_flood_on_uc_dram_ecc_err & 0x1) << 2;
-				pci_write_config32(dev, 0x44, dword);
-			}
    	}
    }
 #endif
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
index 65de0f8..203d112 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
@@ -264,6 +264,15 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
    			/* Clear MC4 error status */
    			pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0);
    			pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0);
+
+				/* Restore MCA settings */
+				if (pDCTstat->mca_config_backed_up) {
+					val = pci_read_config32(pDCTstat->dev_nbmisc, 0x44);
+					val |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30;
+					val |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21;
+					val |= (pDCTstat->sync_flood_on_uc_dram_ecc_err & 0x1) << 2;
+					pci_write_config32(pDCTstat->dev_nbmisc, 0x44, val);
+				}
    		}
    	}
    }