[L] Change in coreboot[main]: acpi: Add acpigen_write_OSC_pci_domain

[Nico Huber (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Johnny Lin, Jonathan Zhang, Lance Zhao, Shuo Liu, Tim Chu, Tim Wawrzynczak.

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81375?usp=email )

Change subject: acpi: Add acpigen_write_OSC_pci_domain
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Patch Set 12:

(2 comments)

File src/acpi/acpigen_pci.c:

https://review.coreboot.org/c/coreboot/+/81375/comment/2c9bbe57_6b47ff85 :
PS12, Line 272: |=
> Why the `or`? Isn't `RETE` still the original input dword0?

I see `RETE` is initially set to `0`. But the `|=` still seems odd (given
how the code is guarded currently, see also other comment about PCIe bits
in the CXL case).

https://review.coreboot.org/c/coreboot/+/81375/comment/d16868fe_7e7e1acb :
PS12, Line 317: 	acpigen_write_create_dword_field(LOCAL7_OP, 0x10, "OTRC");
What about the PCIe fields? On this path, it seems we would return CTRL unaltered.
This seems to be an issue because the code generated by acpigen_OSC_handle_pcie_request()
is always guarded by the PCI UUID, which is probably wrong.