Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Nick Vaccaro, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51374 )
Change subject: soc/intel/common/../car: Calculate SF Mask#1 based on MSR 0xc87 ......................................................................
Patch Set 5:
(2 comments)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/51374/comment/22d750bc_d3c75e02 PS5, Line 520: mov %ecx, %edi
suggestion: […]
Ack
https://review.coreboot.org/c/coreboot/+/51374/comment/9eb88c4f_97aed9d3 PS5, Line 524: (1 << data_ways)
If that is how the register should be programmed, then yeah I guess so 😊 […]
result of two below operations would be different 1. SF_MASK_1 = (1 << (SFWayCnt - data_ways)) - 1 2. SF_MASK_1 = (1 << SFWayCnt) - (1 << data_ways) - 1
Assume SFWayCnt = 0xC and data_ways = 1 then #1 SF_MASK_1 = ( 1 << (0xC - 1)) - 1 = ( 1 << 0xB) - 1 = 7ff #2 SF_MASK_1 = (1 << 0xC) - (1 << 0x1) - 1 = 0x1000 - 2 - 1 = 0xffd
I guess #2 is correct, but I'm seeing a hang,
Looking at cache document, I guess formula is as below.
SF_MASK_1 = ((1 << SFWayCnt) - 1) - ((1 << data_ways) - 1) SF_MASK_1 = ((1 << 0xC) - 1) - ((1 << 0x1) - 1) = (0x1000 - 1) - (2 - 1) = 0xFFF - 1 = 0xFFE
I need to test the code and update the CL again. Suddenly my remote board connect got drop. I will resume debug on Monday. Sorry for delay.