Change in coreboot[master]: soc/intel/common: Add DDR5 and LPDDR5 into the SMBIOS table

[Angel Pons (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Jingle Hsu, Subrata Banik, Patrick Rudolph.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58576 )

Change subject: soc/intel/common: Add DDR5 and LPDDR5 into the SMBIOS table
......................................................................

Patch Set 1:

(1 comment)

File src/soc/intel/common/smbios.c:

https://review.coreboot.org/c/coreboot/+/58576/comment/178d6d03_76c2d48b 
PS1, Line 84: 			dimm->bus_width |= 0x10;
> That's what it appeared to me when I was referring the SPD spec for DDR5 and LP5 […]

OK, I just had a look at the code. The `bus_width` field uses the SMBIOS encoding. The original `0x8` corresponds to the `BIOS_MEMORY_ECC_SINGLE_BIT_CORRECTING` macro. `0x10` corresponds to the `BIOS_MEMORY_ECC_DOUBLE_BIT_CORRECTING` macro. This doesn't need to be changed.