[L] Change in coreboot[main]: acpi: Add PPTT support

[David Milosevic (Code Review)]

Attention is currently required from: Arthur Heymans, Cliff Huang, Lance Zhao, Martin L Roth, Maximilian Brune, Nico Huber, Patrick Rudolph, Tim Wawrzynczak.

David Milosevic has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78071?usp=email )

Change subject: acpi: Add PPTT support
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Patch Set 19:

(1 comment)

File src/acpi/acpi_pptt.c:

https://review.coreboot.org/c/coreboot/+/78071/comment/30e5e7e5_996018ba :
PS17, Line 131: cache_reference_t cache_refs[CONFIG_ACPI_PPTT_MAX_CACHES];
> But doesn't this suffer from the huge list size like you described above?

As Arthur mentioned, in a typical scenario, caches should be the same for each CPU, thus the current code would compact them.

In a non-typical scenario, one would have to increase CONFIG_ACPI_PPTT_MAX_CACHES. It currently defaults to 4 distinct caches per topology level.

I hope that this is a sane value for most scenarios. On the qemu-sbsa we have 3 distinct caches (L1I, L1D, L2). Should we maybe increase the default?

Regarding the depth of the tree, I think this value is kinda limited, if we look at a typical setup (socket, cluster, cpu, thread). That would mean there are 4 topology levels in total, which should be fine.
> (I find this hard to discuss btw. when numbers are hidden in undisclosed

patches.)

I will try to publish the PPTT platform code for qemu-sbsa today/tomorrow. Should be easier then to follow :)