[S] Change in coreboot[master]: soc/amd/mendocino: Add UPDs for DPTC current limits

[Patrick Huang (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Fred Reitberger, Patrick Huang.

Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/73875

to look at the new patch set (#2).

Change subject: soc/amd/mendocino: Add UPDs for DPTC current limits
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soc/amd/mendocino: Add UPDs for DPTC current limits

Add UPD vrm_current_limit_mA, vrm_maximum_current_limit_mA, vrm_soc_current_limit_mA for DPTC.
Make sure UPD parameterare are set to be aligned.

BUG=b:245942343
BRANCH=none
TEST=confirm the UPD parameters has been set correspondingly with the FSP UPD.

Change-Id: Iacf0ce0d51d4c8698ec1ae7e810fd00574deeadb
Signed-off-by: Patrick Huang 
---
M src/vendorcode/amd/fsp/mendocino/FspmUpd.h
1 file changed, 21 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/73875/2