Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36911 )
Change subject: mb/lenovo/x201: Remove unnecessary PMH7 bits ......................................................................
mb/lenovo/x201: Remove unnecessary PMH7 bits
The bits cleared by this mostly have to do with dGPU power, which this board lacks.
TESTED: x201 still boots.
Change-Id: I441743f76afc7bbbee930a1c8116035e85d94e52 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x201/romstage.c 1 file changed, 0 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/36911/1
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index c8e8afb..58e34c8 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -55,9 +55,6 @@
void mainboard_pre_raminit(void) { - outb(0x50, 0x15ec); - outb(inb(0x15ee) & 0x70, 0x15ee); - set_fsb_frequency(); }
Hello Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36911
to look at the new patch set (#2).
Change subject: mb/lenovo/x201: Remove dGPU PMH7 bits ......................................................................
mb/lenovo/x201: Remove dGPU PMH7 bits
The bits cleared by this have to do with dGPU power, which this board lacks.
TESTED: x201 still boots.
Change-Id: I441743f76afc7bbbee930a1c8116035e85d94e52 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x201/romstage.c 1 file changed, 0 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/36911/2
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36911 )
Change subject: mb/lenovo/x201: Remove dGPU PMH7 bits ......................................................................
Patch Set 2: Code-Review+2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36911 )
Change subject: mb/lenovo/x201: Remove dGPU PMH7 bits ......................................................................
Patch Set 2:
How do we know that this doesn't make a difference? Maybe the PMH7 likes the state set up here more if there is no dGPU?
Alexander Couzens has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36911 )
Change subject: mb/lenovo/x201: Remove dGPU PMH7 bits ......................................................................
Patch Set 2: Code-Review+2
Alexander Couzens has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36911 )
Change subject: mb/lenovo/x201: Remove dGPU PMH7 bits ......................................................................
mb/lenovo/x201: Remove dGPU PMH7 bits
The bits cleared by this have to do with dGPU power, which this board lacks.
TESTED: x201 still boots.
Change-Id: I441743f76afc7bbbee930a1c8116035e85d94e52 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/36911 Reviewed-by: Patrick Rudolph siro@das-labor.org Reviewed-by: Alexander Couzens lynxis@fe80.eu Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/lenovo/x201/romstage.c 1 file changed, 0 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Alexander Couzens: Looks good to me, approved Patrick Rudolph: Looks good to me, approved
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 7bab957..aec63db 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -54,9 +54,6 @@
void mainboard_pre_raminit(void) { - outb(0x50, 0x15ec); - outb(inb(0x15ee) & 0x70, 0x15ee); - set_fsb_frequency(); }
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36911 )
Change subject: mb/lenovo/x201: Remove dGPU PMH7 bits ......................................................................
Patch Set 3:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/283 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/282 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/281
Please note: This test is under development and might not be accurate at all!
Alexander Couzens has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36911 )
Change subject: mb/lenovo/x201: Remove dGPU PMH7 bits ......................................................................
Patch Set 3:
We don't need this. The command writes the register 0x50 -> &= 0x70. So it zeroes the bits 0-2 (reserved), 3 (GFXD_ON), 7 (GPURST_N). Bit 3 seems to map to thinker1 pin 66, which is NC. bit 7 seems to map to pin 98 which is connect via 10k resistor to VCC 3.3V.
So it's save not to set it. The default for bit 3 and 7 is 1 btw.
-
9elements QA (Code Review) -
Alexander Couzens (Code Review)
-
Arthur Heymans (Code Review)
-
Nico Huber (Code Review)
-
Patrick Rudolph (Code Review)