Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64010 )
Change subject: nb/amd/agesa/family14: Avoid caching fx devices ......................................................................
nb/amd/agesa/family14: Avoid caching fx devices
Avoid caching fx devices to simplify the code. Ideally, these fx devices would have their own PCI driver to avoid having to get them from another PCI device's own driver.
Change-Id: Ifc6510c00e2b1e46b35dea85199c7c73d75226f7 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/amd/agesa/family14/northbridge.c 1 file changed, 31 insertions(+), 71 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/64010/1
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 4737b19..0fb5b4f 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -18,9 +18,15 @@ #include <northbridge/amd/agesa/agesa_helper.h> #include <sb_cimx.h>
-static struct device *__f0_dev; -static struct device *__f1_dev; -static unsigned int fx_devs = 0; +static struct device *get_fx_dev(u8 func) +{ + struct device *dev = pcidev_on_root(DEV_CDB, func); + + if (!dev) + die("Cannot find 0:0x%x.%u\n", DEV_CDB, func); + + return dev; +}
static u32 get_io_addr_index(u32 nodeid, u32 linkn) { @@ -35,74 +41,37 @@ static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max) { + struct device *f1_dev = get_fx_dev(1);
u32 tempreg; /* io range allocation */ tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | ((io_max & 0xf0) << (12 - 4)); //limit - pci_write_config32(__f1_dev, reg+4, tempreg); + pci_write_config32(f1_dev, reg+4, tempreg);
tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); //base :ISA and VGA ? - pci_write_config32(__f1_dev, reg, tempreg); + pci_write_config32(f1_dev, reg, tempreg); }
static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) { + struct device *f1_dev = get_fx_dev(1);
u32 tempreg; /* io range allocation */ tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); - pci_write_config32(__f1_dev, reg + 4, tempreg); + pci_write_config32(f1_dev, reg + 4, tempreg); tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00); - pci_write_config32(__f1_dev, reg, tempreg); -} - -static void get_fx_devs(void) -{ - if (fx_devs) - return; - - __f0_dev = pcidev_on_root(DEV_CDB, 0); - __f1_dev = pcidev_on_root(DEV_CDB, 1); - - if (__f0_dev == NULL || __f1_dev == NULL) { - die("Cannot find 0:0x18.[0|1]\n"); - } - - fx_devs = 1; -} - -static u32 f1_read_config32(unsigned int reg) -{ - if (fx_devs == 0) - get_fx_devs(); - return pci_read_config32(__f1_dev, reg); -} - -static void f1_write_config32(unsigned int reg, u32 value) -{ - int i; - if (fx_devs == 0) - get_fx_devs(); - for (i = 0; i < fx_devs; i++) { - struct device *dev; - dev = __f1_dev; - if (dev && dev->enabled) { - pci_write_config32(dev, reg, value); - } - } + pci_write_config32(f1_dev, reg, tempreg); }
static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk) { + struct device *f1_dev = get_fx_dev(1); u32 temp;
- if (fx_devs == 0) - get_fx_devs(); - - - temp = pci_read_config32(__f1_dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] + temp = pci_read_config32(f1_dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] if (!(temp & 1)) return 0; // this memory range is not enabled /* @@ -114,7 +83,7 @@ * BKDG address[35:0] <= {DramLimit[35:24], FF_FFFFh} converted as above but * ORed with 0xffff to get real limit before shifting. */ - temp = pci_read_config32(__f1_dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] + temp = pci_read_config32(f1_dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] *limitk = ((temp & 0x0fff0000) | 0xffff) >> (10 - 8); *limitk += 1; // round up last byte
@@ -138,7 +107,7 @@ val = 1 | (nodeid << 4) | (linkn << 12); /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb, 0x3c0:0x3df */ - f1_write_config32(0xf4, val); + pci_write_config32(get_fx_dev(1), 0xf4, val);
}
@@ -149,11 +118,8 @@ unsigned int nodeid, link = 0; int result; res = 0; - for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device *dev; - dev = __f0_dev; - if (!dev) - continue; + for (nodeid = 0; !res && (nodeid < 1); nodeid++) { + struct device *dev = get_fx_dev(0); for (link = 0; !res && (link < 8); link++) { res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); } @@ -303,7 +269,7 @@ u32 hole;
if (get_dram_base_limit(0, &basek, &limitk)) { - hole = pci_read_config32(__f1_dev, 0xf0); + hole = pci_read_config32(get_fx_dev(1), 0xf0); if (hole & 1) { // we find the hole mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; mem_hole.node_id = 0; // record the node No with hole @@ -454,27 +420,21 @@ printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__);
/* Find the already assigned resource pairs */ - get_fx_devs(); + struct device *f1_dev = get_fx_dev(1); for (reg = 0x80; reg <= 0xc0; reg += 0x08) { u32 base, limit; - base = f1_read_config32(reg); - limit = f1_read_config32(reg + 0x04); + base = pci_read_config32(f1_dev, reg); + limit = pci_read_config32(f1_dev, reg + 0x04); /* Is this register allocated? */ if ((base & 3) != 0) { unsigned int reg_link; - struct device *reg_dev; + struct device *reg_dev = get_fx_dev(0); reg_link = (limit >> 4) & 7; - reg_dev = __f0_dev; - if (reg_dev) { - /* Reserve the resource */ - struct resource *res; - res = - new_resource(reg_dev, - IOINDEX(0x1000 + reg, - reg_link)); - if (res) { - res->flags = 1; - } + /* Reserve the resource */ + struct resource *res; + res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); + if (res) { + res->flags = 1; } } }