Change in coreboot[master]: mb/adlrvp: Fix DDR5 Boot issue

[Subrata Banik (Code Review)]

Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Meera Ravindranath, Angel Pons, Patrick Rudolph.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50996 )

Change subject: mb/adlrvp: Fix DDR5 Boot issue
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Patch Set 19:

(1 comment)

File src/soc/intel/alderlake/meminit.c:

https://review.coreboot.org/c/coreboot/+/50996/comment/5637d22a_39009b77 
PS19, Line 260: smbus_address_valid = true;
> DDR5 can be either memory-down or DIMMs. […]

+2 on splitting the code nicely between mainboard and SoC, i was not very happy to hardcode SMBUS address in SoC code earlier.

Just one question for Furquan on board design side, so you see DDR5 memory's are soldered down on always socketed on ref design? if both possible then ".topo" make sense to me.