Change in coreboot[master]: nb/intel/x4x: Issue a hard reset with empty MRC cache on warm reset

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27100

Change subject: nb/intel/x4x: Issue a hard reset with empty MRC cache on warm reset
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nb/intel/x4x: Issue a hard reset with empty MRC cache on warm reset

The dram controller cannot fully initialize the memory controller on
warm reset (receive enable calibration consistently fails).

This option is mostly useful when rebooting after having flashed a new
rom which overwrites the mrc cache region.

Change-Id: I405c0eca076fe081641ede9a670f734c98cbf8fc
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/x4x/raminit.c
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/27100/1

diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index d41b74c..30c6477 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -653,6 +653,9 @@
    		/* Failed S3 resume, reset to come up cleanly */
    		outb(0x6, 0xcf9);
    		halt();
+		} else if (boot_path == BOOT_PATH_WARM_RESET) {
+			outb(0xe, 0xcf9);
+			halt();
    	}
    	ctrl_cached = NULL;
    } else {