EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47912 )
Change subject: mb/google/zork/var/vliboz: Add LTE_RST power sequence ......................................................................
mb/google/zork/var/vliboz: Add LTE_RST power sequence
Latest HW schematic add LTE_RST pin to control module power sequence.
BUG=b:173490220 BRANCH=zork TEST=measure the waveform is meet the LTE module spec.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0f0a35a905d711dd8d17dea2ae82a8dfa1fa05ed --- M src/mainboard/google/zork/smihandler.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/zork/variants/vilboz/Makefile.inc M src/mainboard/google/zork/variants/vilboz/gpio.c M src/mainboard/google/zork/variants/vilboz/variant.c 5 files changed, 52 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/47912/1
diff --git a/src/mainboard/google/zork/smihandler.c b/src/mainboard/google/zork/smihandler.c index 1c26d45..0b732a8 100644 --- a/src/mainboard/google/zork/smihandler.c +++ b/src/mainboard/google/zork/smihandler.c @@ -10,11 +10,17 @@ #include <variant/gpio.h> #include <console/console.h>
+void __weak variant_smi_sleep(u8 slp_typ) +{ + /* Leave for the variant to implement if necessary. */ +} + void mainboard_smi_gpi(u32 gpi_sts) { if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_process_events(); } + void mainboard_smi_sleep(u8 slp_typ) { size_t num_gpios; @@ -26,6 +32,8 @@
gpios = variant_sleep_gpio_table(&num_gpios, slp_typ); program_gpios(gpios, num_gpios); + + variant_smi_sleep(slp_typ); }
int mainboard_smi_apmc(u8 apmc) diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 4ec6add..3a360a8 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -82,5 +82,7 @@ bool variant_has_fingerprint(void); /* Return true if the board needs an extra fpmcu delay. */ bool fpmcu_needs_delay(void); +/* allow each variants to customize smi sleep flow. */ +void variant_smi_sleep(u8 slp_typ);
#endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/zork/variants/vilboz/Makefile.inc b/src/mainboard/google/zork/variants/vilboz/Makefile.inc index af38c88..963eee4 100644 --- a/src/mainboard/google/zork/variants/vilboz/Makefile.inc +++ b/src/mainboard/google/zork/variants/vilboz/Makefile.inc @@ -4,3 +4,5 @@
ramstage-y += variant.c ramstage-y += gpio.c + +smm-y += variant.c diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c index 6fba0e2..3ce59db 100644 --- a/src/mainboard/google/zork/variants/vilboz/gpio.c +++ b/src/mainboard/google/zork/variants/vilboz/gpio.c @@ -19,6 +19,29 @@ static const struct soc_amd_gpio vilboz_gpio_set_stage_ram[] = { /* P sensor INT */ PAD_INT(GPIO_40, PULL_NONE, LEVEL_LOW, STATUS_DELIVERY), + /* LTE_FW_RST_L */ + PAD_GPO(GPIO_89, HIGH), +}; + +static const struct soc_amd_gpio vilboz_early_gpio_table[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* PCIE_RST0_L - Fixed timings */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), + /* LTE_FW_RST_L */ + PAD_GPO(GPIO_89, LOW), };
const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) @@ -41,3 +64,9 @@ *size = ARRAY_SIZE(vilboz_gpio_set_stage_ram); return vilboz_gpio_set_stage_ram; } + +const struct soc_amd_gpio *variant_early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(vilboz_early_gpio_table); + return vilboz_early_gpio_table; +} diff --git a/src/mainboard/google/zork/variants/vilboz/variant.c b/src/mainboard/google/zork/variants/vilboz/variant.c index cbc160e..3d587cc 100644 --- a/src/mainboard/google/zork/variants/vilboz/variant.c +++ b/src/mainboard/google/zork/variants/vilboz/variant.c @@ -1,6 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <acpi/acpi.h> #include <baseboard/variants.h> +#include <gpio.h> +#include <soc/gpio.h> #include <soc/pci_devs.h>
static const fsp_ddi_descriptor hdmi_ddi_descriptors[] = { @@ -31,3 +34,11 @@ *ddi_descs = &hdmi_ddi_descriptors[0]; *ddi_num = ARRAY_SIZE(hdmi_ddi_descriptors); } + +void variant_smi_sleep(u8 slp_typ) +{ + if (slp_typ == ACPI_S5) { + /* Assert LTE_FW_RST_L */ + gpio_output(GPIO_89, 0); + } +}
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47912 )
Change subject: mb/google/zork/var/vliboz: Add LTE_RST power sequence ......................................................................
Patch Set 1:
@Furquan, please give some feedback on this. Basically follow the octopus LTE power sequence but FPO is controlled by EC. So just add RST pin part in coreboot. CB:45193 I think early table is not needed, will update this after HW measure it.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47912 )
Change subject: mb/google/zork/var/vliboz: Add LTE_RST power sequence ......................................................................
Set Ready For Review
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47912 )
Change subject: mb/google/zork/var/vliboz: Add LTE_RST power sequence ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47912/1/src/mainboard/google/zork/v... File src/mainboard/google/zork/variants/vilboz/variant.c:
https://review.coreboot.org/c/coreboot/+/47912/1/src/mainboard/google/zork/v... PS1, Line 42: GPIO_89
SG, will discuss with HW and do some experiments. […]
It worked if we add pull-down for it:)
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47912 )
Change subject: mb/google/zork/var/vliboz: Add LTE_RST power sequence ......................................................................
Patch Set 2:
@Furquan, we need some delay here, can I just put the delay before return? Need about 20ms to meet the spec..
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47912 )
Change subject: mb/google/zork/var/vliboz: Add LTE_RST power sequence ......................................................................
Patch Set 2:
Patch Set 2:
@Furquan, we need some delay here, can I just put the delay before return? Need about 20ms to meet the spec..
Delay of 20ms between what actions?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47912 )
Change subject: mb/google/zork/var/vliboz: Add LTE_RST power sequence ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2:
@Furquan, we need some delay here, can I just put the delay before return? Need about 20ms to meet the spec..
Delay of 20ms between what actions?
Between wwan power on, and it control by EC, so the power on sequence will driver after SLP_S3 high.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47912 )
Change subject: mb/google/zork/var/vliboz: Add LTE_RST power sequence ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2:
Patch Set 2:
@Furquan, we need some delay here, can I just put the delay before return? Need about 20ms to meet the spec..
Delay of 20ms between what actions?
Between wwan power on, and it control by EC, so the power on sequence will driver after SLP_S3 high.
If WWAN power on happens on SLP_S3# deassertion, then there is no need to add an additional 20ms delay. LTE_RST_L# is deasserted in ramstage which is guaranteed to be much greater than 20ms.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47912 )
Change subject: mb/google/zork/var/vliboz: Add LTE_RST power sequence ......................................................................
Patch Set 2:
This is hypothesis question. HW is checking with vendor now. If we get luck, no need delay here :)
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47912 )
Change subject: mb/google/zork/var/vliboz: Add LTE_RST power sequence ......................................................................
Patch Set 2: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47912 )
Change subject: mb/google/zork/var/vliboz: Add LTE_RST power sequence ......................................................................
Patch Set 2:
Patch Set 2:
This is hypothesis question. HW is checking with vendor now. If we get luck, no need delay here :)
Oh okay. Yeah, as you mentioned, if the power is controlled by SLP_S3# we don't need to worry about the 20ms delay.
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47912 )
Change subject: mb/google/zork/var/vliboz: Add LTE_RST power sequence ......................................................................
mb/google/zork/var/vliboz: Add LTE_RST power sequence
Latest HW schematic add LTE_RST pin to control module power sequence.
BUG=b:173490220 BRANCH=zork TEST=measure the waveform is meet the LTE module spec.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0f0a35a905d711dd8d17dea2ae82a8dfa1fa05ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/47912 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/zork/variants/vilboz/gpio.c 1 file changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c index 6fba0e2..c6ef161 100644 --- a/src/mainboard/google/zork/variants/vilboz/gpio.c +++ b/src/mainboard/google/zork/variants/vilboz/gpio.c @@ -19,6 +19,8 @@ static const struct soc_amd_gpio vilboz_gpio_set_stage_ram[] = { /* P sensor INT */ PAD_INT(GPIO_40, PULL_NONE, LEVEL_LOW, STATUS_DELIVERY), + /* LTE_RST_L */ + PAD_GPO(GPIO_89, HIGH), };
const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
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EricR Lai (Code Review) -
Furquan Shaikh (Code Review)
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Patrick Georgi (Code Review)