Change in coreboot[master]: soc/intel/cnl: Add CML GT IDs

[Meera Ravindranath (Code Review)]

Hello Usha P,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/35120

to review the following change.

Change subject: soc/intel/cnl: Add CML GT IDs
......................................................................

soc/intel/cnl: Add CML GT IDs

TEST=Build and boot CMLRVP.

Change-Id: Ib79995606f6da12bfa7aa5c1a1dbc0b972bb1688
Signed-off-by: Meera Ravindranath 
Signed-off-by: Usha P 
---
M src/include/device/pci_ids.h
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/common/block/graphics/graphics.c
3 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/35120/1

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index cdd1c62..5ad61e0 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3083,6 +3083,8 @@
 #define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_2		0x9B4A
 #define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_3		0x9B2B
 #define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4		0x9B2C
+#define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5		0x9BAA
+#define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_6		0x9BCA
 #define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3		0x9B4B
 #define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4		0x9B4C
 #define PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1		0x9B20
diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c
index de2feaf..67d991c 100644
--- a/src/soc/intel/cannonlake/bootblock/report_platform.c
+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c
@@ -135,6 +135,8 @@
    { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4, "CometLake ULT GT1" },
    { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3, "CometLake ULT GT2" },
    { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4, "CometLake ULT GT2" },
+	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5, "CometLake ULT GT2" },
+	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_6, "CometLake ULT GT2" }
    { PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1, "CometLake ULX GT1" },
    { PCI_DEVICE_ID_INTEL_CML_GT2_ULX_1, "CometLake ULX GT2" },
    { PCI_DEVICE_ID_INTEL_CML_GT1_S_1, "CometLake S GT1" },
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 2b4c4a7..7aece76 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -177,6 +177,8 @@
    PCI_DEVICE_ID_INTEL_CML_GT2_ULT_2,
    PCI_DEVICE_ID_INTEL_CML_GT1_ULT_3,
    PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4,
+	PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5,
+	PCI_DEVICE_ID_INTEL_CML_GT2_ULT_6,
    PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3,
    PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4,
    PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1,

[Subrata Banik (Code Review)]

Subrata Banik has uploaded a new patch set (#2) to the change originally created by Meera Ravindranath. ( https://review.coreboot.org/c/coreboot/+/35120 )

Change subject: soc/intel/cnl: Add CML GT IDs
......................................................................

soc/intel/cnl: Add CML GT IDs

TEST=Build and boot CMLRVP.

Change-Id: Ib79995606f6da12bfa7aa5c1a1dbc0b972bb1688
Signed-off-by: Meera Ravindranath 
Signed-off-by: Usha P 
---
M src/include/device/pci_ids.h
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/common/block/graphics/graphics.c
3 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/35120/2

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35120 )

Change subject: soc/intel/cnl: Add CML GT IDs
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35120/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/35120/2//COMMIT_MSG@7 
PS2, Line 7: GT 
IGD

[Meera Ravindranath (Code Review)]

Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35120 )

Change subject: soc/intel/cnl: Add CML GT IDs
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35120/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/35120/2//COMMIT_MSG@7 
PS2, Line 7: GT
> IGD

Ack

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35120 )

Change subject: soc/intel/cnl: Add CML GT IDs
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35120/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/35120/2//COMMIT_MSG@7 
PS2, Line 7: GT
> Ack

can you please update commit msg with IGD IDs.

Change in coreboot[master]: soc/intel/cnl: Add CML IGD IDs

[Meera Ravindranath (Code Review)]

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Ronak Kanabar, Aamir Bohra, Usha P, Maulik V Vaghela, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35120

to look at the new patch set (#3).

Change subject: soc/intel/cnl: Add CML IGD IDs
......................................................................

soc/intel/cnl: Add CML IGD IDs

TEST=Build and boot CMLRVP.

Change-Id: Ib79995606f6da12bfa7aa5c1a1dbc0b972bb1688
Signed-off-by: Meera Ravindranath 
Signed-off-by: Usha P 
---
M src/include/device/pci_ids.h
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/common/block/graphics/graphics.c
3 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/35120/3

Change in coreboot[master]: soc/intel/cnl: Add CML IGD IDs

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35120 )

Change subject: soc/intel/cnl: Add CML IGD IDs
......................................................................

Patch Set 3: Code-Review+2

Change in coreboot[master]: soc/intel/cnl: Add CML IGD IDs

[Meera Ravindranath (Code Review)]

Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35120 )

Change subject: soc/intel/cnl: Add CML IGD IDs
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35120/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/35120/2//COMMIT_MSG@7 
PS2, Line 7: GT
> can you please update commit msg with IGD IDs.

Done

Change in coreboot[master]: soc/intel/cnl: Add CML IGD IDs

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35120 )

Change subject: soc/intel/cnl: Add CML IGD IDs
......................................................................

Patch Set 3:

may be good to add bug as b:139798422 to track this effort ?

Change in coreboot[master]: soc/intel/cnl: Add CML IGD IDs

[Meera Ravindranath (Code Review)]

Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35120 )

Change subject: soc/intel/cnl: Add CML IGD IDs
......................................................................

Patch Set 3:
> Patch Set 3:
>
> may be good to add bug as b:139798422 to track this effort ?

Okay. Will add!

Change in coreboot[master]: soc/intel/cnl: Add CML IGD IDs

[Meera Ravindranath (Code Review)]

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Ronak Kanabar, Aamir Bohra, Usha P, Maulik V Vaghela, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35120

to look at the new patch set (#4).

Change subject: soc/intel/cnl: Add CML IGD IDs
......................................................................

soc/intel/cnl: Add CML IGD IDs

BUG=b:139798422
TEST=Build and boot CMLRVP.

Change-Id: Ib79995606f6da12bfa7aa5c1a1dbc0b972bb1688
Signed-off-by: Meera Ravindranath 
Signed-off-by: Usha P 
---
M src/include/device/pci_ids.h
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/common/block/graphics/graphics.c
3 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/35120/4

Change in coreboot[master]: soc/intel/cnl: Add CML IGD IDs

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35120 )

Change subject: soc/intel/cnl: Add CML IGD IDs
......................................................................

Patch Set 4: Code-Review+2

Change in coreboot[master]: soc/intel/cnl: Add CML IGD IDs

[Meera Ravindranath (Code Review)]

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Ronak Kanabar, Aamir Bohra, Usha P, Maulik V Vaghela, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35120

to look at the new patch set (#5).

Change subject: soc/intel/cnl: Add CML IGD IDs
......................................................................

soc/intel/cnl: Add CML IGD IDs

BUG=b:139798422
TEST=Build and boot CMLRVP.

Change-Id: Ib79995606f6da12bfa7aa5c1a1dbc0b972bb1688
Signed-off-by: Meera Ravindranath 
Signed-off-by: Usha P 
---
M src/include/device/pci_ids.h
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/common/block/graphics/graphics.c
3 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/35120/5

Change in coreboot[master]: soc/intel/cnl: Add CML IGD IDs

[Meera Ravindranath (Code Review)]

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Ronak Kanabar, Aamir Bohra, Usha P, Maulik V Vaghela, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35120

to look at the new patch set (#6).

Change subject: soc/intel/cnl: Add CML IGD IDs
......................................................................

soc/intel/cnl: Add CML IGD IDs

BUG=b:139798422
TEST=Build and boot CMLRVP.

Change-Id: Ib79995606f6da12bfa7aa5c1a1dbc0b972bb1688
Signed-off-by: Meera Ravindranath 
Signed-off-by: Usha P 
---
M src/include/device/pci_ids.h
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/common/block/graphics/graphics.c
3 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/35120/6

Change in coreboot[master]: soc/intel/cnl: Add CML IGD IDs

[V Sowmya (Code Review)]

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35120 )

Change subject: soc/intel/cnl: Add CML IGD IDs
......................................................................

Patch Set 6: Code-Review+2

Change in coreboot[master]: soc/intel/cnl: Add CML IGD IDs

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35120 )

Change subject: soc/intel/cnl: Add CML IGD IDs
......................................................................

Patch Set 6: Code-Review+2

Change in coreboot[master]: soc/intel/cnl: Add CML IGD IDs

[Ronak Kanabar (Code Review)]

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35120 )

Change subject: soc/intel/cnl: Add CML IGD IDs
......................................................................

Patch Set 6: Code-Review+2

Change in coreboot[master]: soc/intel/cnl: Add CML IGD IDs

[Lance Zhao (Code Review)]

Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35120 )

Change subject: soc/intel/cnl: Add CML IGD IDs
......................................................................

Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35120/6/src/soc/intel/cannonlake/bo... 
File src/soc/intel/cannonlake/bootblock/report_platform.c:

https://review.coreboot.org/c/coreboot/+/35120/6/src/soc/intel/cannonlake/bo... 
PS6, Line 130: 	{ PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1, "CometLake ULT GT1" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2, "CometLake ULT GT1" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1, "CometLake ULT GT2" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_2, "CometLake ULT GT2" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT1_ULT_3, "CometLake ULT GT1" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4, "CometLake ULT GT1" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3, "CometLake ULT GT2" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4, "CometLake ULT GT2" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5, "CometLake ULT GT2" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_6, "CometLake ULT GT2" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1, "CometLake ULX GT1" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULX_1, "CometLake ULX GT2" }
Can we have different string that can properly differentiate different device ID?

Change in coreboot[master]: soc/intel/cnl: Add CML IGD IDs

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35120 )

Change subject: soc/intel/cnl: Add CML IGD IDs
......................................................................

Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35120/6/src/soc/intel/cannonlake/bo... 
File src/soc/intel/cannonlake/bootblock/report_platform.c:

https://review.coreboot.org/c/coreboot/+/35120/6/src/soc/intel/cannonlake/bo... 
PS6, Line 130: 	{ PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1, "CometLake ULT GT1" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2, "CometLake ULT GT1" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1, "CometLake ULT GT2" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_2, "CometLake ULT GT2" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT1_ULT_3, "CometLake ULT GT1" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4, "CometLake ULT GT1" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3, "CometLake ULT GT2" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4, "CometLake ULT GT2" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5, "CometLake ULT GT2" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_6, "CometLake ULT GT2" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1, "CometLake ULX GT1" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULX_1, "CometLake ULX GT2" }
> Can we have different string that can properly differentiate different device ID?

@Lance, nice to see you in review :)
As per ID document these are also GT2 parts

Change in coreboot[master]: soc/intel/cnl: Add CML IGD IDs

[Lance Zhao (Code Review)]

Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35120 )

Change subject: soc/intel/cnl: Add CML IGD IDs
......................................................................

Patch Set 6: Code-Review+2

Okay

Change in coreboot[master]: soc/intel/cnl: Add CML IGD IDs

[Meera Ravindranath (Code Review)]

Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35120 )

Change subject: soc/intel/cnl: Add CML IGD IDs
......................................................................

Patch Set 6:

(1 comment)
> Patch Set 3:
>
> may be good to add bug as b:139798422 to track this effort ?

https://review.coreboot.org/c/coreboot/+/35120/6/src/soc/intel/cannonlake/bo... 
File src/soc/intel/cannonlake/bootblock/report_platform.c:

https://review.coreboot.org/c/coreboot/+/35120/6/src/soc/intel/cannonlake/bo... 
PS6, Line 130: 	{ PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1, "CometLake ULT GT1" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2, "CometLake ULT GT1" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1, "CometLake ULT GT2" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_2, "CometLake ULT GT2" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT1_ULT_3, "CometLake ULT GT1" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4, "CometLake ULT GT1" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3, "CometLake ULT GT2" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4, "CometLake ULT GT2" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5, "CometLake ULT GT2" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_6, "CometLake ULT GT2" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1, "CometLake ULX GT1" },
             : 	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULX_1, "CometLake ULX GT2" }
> @Lance, nice to see you in review :) […]

Done

Change in coreboot[master]: soc/intel/cnl: Add CML IGD IDs

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/35120 )

Change subject: soc/intel/cnl: Add CML IGD IDs
......................................................................

soc/intel/cnl: Add CML IGD IDs

BUG=b:139798422
TEST=Build and boot CMLRVP.

Change-Id: Ib79995606f6da12bfa7aa5c1a1dbc0b972bb1688
Signed-off-by: Meera Ravindranath 
Signed-off-by: Usha P 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35120
Tested-by: build bot (Jenkins) 
Reviewed-by: V Sowmya 
Reviewed-by: Subrata Banik 
Reviewed-by: Ronak Kanabar 
Reviewed-by: Lance Zhao 
---
M src/include/device/pci_ids.h
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/common/block/graphics/graphics.c
3 files changed, 6 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  V Sowmya: Looks good to me, approved
  Lance Zhao: Looks good to me, approved
  Ronak Kanabar: Looks good to me, approved

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index cdd1c62..5ad61e0 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3083,6 +3083,8 @@
 #define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_2		0x9B4A
 #define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_3		0x9B2B
 #define PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4		0x9B2C
+#define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5		0x9BAA
+#define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_6		0x9BCA
 #define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3		0x9B4B
 #define PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4		0x9B4C
 #define PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1		0x9B20
diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c
index de2feaf..3d46916 100644
--- a/src/soc/intel/cannonlake/bootblock/report_platform.c
+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c
@@ -135,6 +135,8 @@
    { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4, "CometLake ULT GT1" },
    { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3, "CometLake ULT GT2" },
    { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4, "CometLake ULT GT2" },
+	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5, "CometLake ULT GT2" },
+	{ PCI_DEVICE_ID_INTEL_CML_GT2_ULT_6, "CometLake ULT GT2" },
    { PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1, "CometLake ULX GT1" },
    { PCI_DEVICE_ID_INTEL_CML_GT2_ULX_1, "CometLake ULX GT2" },
    { PCI_DEVICE_ID_INTEL_CML_GT1_S_1, "CometLake S GT1" },
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 2b4c4a7..7aece76 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -177,6 +177,8 @@
    PCI_DEVICE_ID_INTEL_CML_GT2_ULT_2,
    PCI_DEVICE_ID_INTEL_CML_GT1_ULT_3,
    PCI_DEVICE_ID_INTEL_CML_GT1_ULT_4,
+	PCI_DEVICE_ID_INTEL_CML_GT2_ULT_5,
+	PCI_DEVICE_ID_INTEL_CML_GT2_ULT_6,
    PCI_DEVICE_ID_INTEL_CML_GT2_ULT_3,
    PCI_DEVICE_ID_INTEL_CML_GT2_ULT_4,
    PCI_DEVICE_ID_INTEL_CML_GT1_ULX_1,

Change in coreboot[master]: soc/intel/cnl: Add CML IGD IDs

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35120 )

Change subject: soc/intel/cnl: Add CML IGD IDs
......................................................................

Patch Set 7:

(5 comments)

https://review.coreboot.org/c/coreboot/+/35120/6/src/soc/intel/cannonlake/bo... 
File src/soc/intel/cannonlake/bootblock/report_platform.c:

https://review.coreboot.org/c/coreboot/+/35120/6/src/soc/intel/cannonlake/bo... 
PS6, Line 31: static struct {
Pull the struct declarations into a common intel/ header file.

https://review.coreboot.org/c/coreboot/+/35120/6/src/soc/intel/cannonlake/bo... 
PS6, Line 34: } cpu_table[] = {
Not the scope of this patch, but why is report_platform and all these strings defined under bootblock/ diretory?

https://review.coreboot.org/c/coreboot/+/35120/6/src/soc/intel/cannonlake/bo... 
PS6, Line 152: static uint8_t get_dev_revision(pci_devfn_t dev)
Why define this? Just call pci_read_config8() directly.

https://review.coreboot.org/c/coreboot/+/35120/6/src/soc/intel/cannonlake/bo... 
PS6, Line 157: static uint16_t get_dev_id(pci_devfn_t dev)
Same thing.

https://review.coreboot.org/c/coreboot/+/35120/6/src/soc/intel/cannonlake/bo... 
PS6, Line 274: void report_platform_info(void)
As far as I can see there is nothing cannonlake specific in these functions, only the tables would change from one SoC to another. Avoid copy-pasting, declare the table structs in common intel header.