[S] Change in coreboot[main]: soc/amd/genoa: set up the non-FCH IOAPICs

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76531?usp=email )

(

6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/amd/genoa: set up the non-FCH IOAPICs
......................................................................

soc/amd/genoa: set up the non-FCH IOAPICs

Apart from the IOAPIC in the FCH which is handled by amd_lpc_ops,
there's one IOAPIC per PCI root which also needs to be initialized.

Signed-off-by: Arthur Heymans 
Change-Id: I38af5a194062e714827852e95f4e29b45311e517
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76531
Tested-by: build bot (Jenkins) 
Reviewed-by: Varshit Pandya 
Reviewed-by: Martin L Roth 
---
M src/soc/amd/genoa/domain.c
1 file changed, 10 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Martin L Roth: Looks good to me, approved
  Varshit Pandya: Looks good to me, approved

diff --git a/src/soc/amd/genoa/domain.c b/src/soc/amd/genoa/domain.c
index 99d7edc..1a6115f 100644
--- a/src/soc/amd/genoa/domain.c
+++ b/src/soc/amd/genoa/domain.c
@@ -48,8 +48,18 @@
    }
 }

+static void genoa_domain_init(struct device *domain)
+{
+	struct resource *res = probe_resource(domain, IOMMU_IOAPIC_IDX);
+	if (!res)
+		return;
+
+	register_new_ioapic((void *)(uintptr_t)res->base);
+}
+
 struct device_operations genoa_pci_domain_ops = {
    .read_resources	= genoa_domain_read_resources,
    .set_resources	= genoa_domain_set_resources,
    .scan_bus	= amd_pci_domain_scan_bus,
+	.init		= genoa_domain_init,
 };