[S] Change in coreboot[main]: soc/intel/xeon_sp/spr: Enable x86_64 support

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81280?usp=email )

(

3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/intel/xeon_sp/spr: Enable x86_64 support
......................................................................

soc/intel/xeon_sp/spr: Enable x86_64 support

Fix compilation errors when compiled for x86_64.

Test: Booted on ibm/sbp1 to linux payload.

Change-Id: I2c5ed0339a9c2e9b088b16dbb4c19df98e796d65
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81280
Reviewed-by: Jérémy Compostella 
Reviewed-by: Shuo Liu 
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
---
M src/soc/intel/xeon_sp/spr/Kconfig
M src/soc/intel/xeon_sp/spr/romstage.c
M src/soc/intel/xeon_sp/spr/upd_display.c
3 files changed, 6 insertions(+), 5 deletions(-)

Approvals:
  Nico Huber: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified
  Jérémy Compostella: Looks good to me, approved
  Shuo Liu: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 3c3c45a..23d2f8b6 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -16,6 +16,7 @@
    select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND
    select UDK_202005_BINDING
    select SOC_INTEL_HAS_CXL
+	select HAVE_EXP_X86_64_SUPPORT
    help
      Intel Sapphire Rapids-SP support

diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c
index 3b38828..91d2099 100644
--- a/src/soc/intel/xeon_sp/spr/romstage.c
+++ b/src/soc/intel/xeon_sp/spr/romstage.c
@@ -114,7 +114,7 @@
 {
    unsigned int port, socket;

-	mupd->FspmConfig.IioPcieConfigTablePtr = (UINT32)spr_iio_bifur_table;
+	mupd->FspmConfig.IioPcieConfigTablePtr = (uintptr_t)spr_iio_bifur_table;
    /* MAX_SOCKET is the maximal number defined by FSP, currently is 4. */
    mupd->FspmConfig.IioPcieConfigTableNumber = MAX_SOCKET;
    UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig =
@@ -130,7 +130,7 @@
    	PciePortConfig[socket].PcieMaxReadRequestSize = 0x5;
    }

-	mupd->FspmConfig.DeEmphasisPtr = (UINT32)deemphasis_list;
+	mupd->FspmConfig.DeEmphasisPtr = (uintptr_t)deemphasis_list;
    mupd->FspmConfig.DeEmphasisNumber = MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET;
    UINT8 *DeEmphasisConfig = (UINT8 *)deemphasis_list;

@@ -287,7 +287,7 @@
    	UPD_IIO_PCIE_PORT_CONFIG *iio_pcie_cfg;
    	int socket;

-		iio_pcie_cfg = (UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr;
+		iio_pcie_cfg = (UPD_IIO_PCIE_PORT_CONFIG *)(uintptr_t)mupd->FspmConfig.IioPcieConfigTablePtr;

for (socket = 0; socket < MAX_SOCKET; socket++)
    		iio_pcie_cfg[socket].PcieGlobalAspm = 0;
diff --git a/src/soc/intel/xeon_sp/spr/upd_display.c b/src/soc/intel/xeon_sp/spr/upd_display.c
index c69a9a0..b3c0c7c 100644
--- a/src/soc/intel/xeon_sp/spr/upd_display.c
+++ b/src/soc/intel/xeon_sp/spr/upd_display.c
@@ -12,7 +12,7 @@
    int port, socket;

UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig =
-		(UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr;
+		(UPD_IIO_PCIE_PORT_CONFIG *)(uintptr_t)mupd->FspmConfig.IioPcieConfigTablePtr;

printk(BIOS_SPEW, "UPD values for IIO:\n");
    for (socket = 0; socket < mupd->FspmConfig.IioPcieConfigTableNumber; socket++) {
@@ -94,7 +94,7 @@
    	       PciePortConfig[socket].PcieMaxReadRequestSize);
    }

-	UINT8 *DeEmphasisConfig = (UINT8 *)mupd->FspmConfig.DeEmphasisPtr;
+	UINT8 *DeEmphasisConfig = (UINT8 *)(uintptr_t)mupd->FspmConfig.DeEmphasisPtr;
    for (port = 0; port < mupd->FspmConfig.DeEmphasisNumber; port++) {
    	printk(BIOS_SPEW, "port: %d, DeEmphasisConfig: 0x%x\n", port,
    	       DeEmphasisConfig[port]);