John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46571 )
Change subject: Retrieve CBI about Retimer and notify TBT firmware ......................................................................
Retrieve CBI about Retimer and notify TBT firmware
Boards might have 20 Gbps or 40 Gbps retimer respectively. It is required to inform Thunderbolt firmware about the Type-C port speed capability. This change retrieves CBI FW_CONFIG tag which has on board retimer setting and notifies LC by programming the dedicated PCIe configuration register. LC delays link establishment until it gets the port speed notification.
BUG=b:163110905 TEST=booted to kernel and validated TCSS functions on Volteer boards which have 20 Gbps and 40 Gbps retimer respectively.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I0bbad465dcab5b44b1ddbd6431391b5a3a18fa12 --- M src/mainboard/google/volteer/mainboard.c 1 file changed, 42 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/46571/1
diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 03a78fd..9a0f5c9 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -4,6 +4,7 @@ #include <acpi/acpi.h> #include <baseboard/variants.h> #include <device/device.h> +#include <device/pci.h> #include <drivers/spi/tpm/tpm.h> #include <ec/ec.h> #include <fw_config.h> @@ -79,19 +80,57 @@ override_pads, override_num); }
+static void mainboard_retimer_notify(struct device *dev, bool usb4_gen) +{ + uint32_t reg32; + + /* + * Program host interface PCIe configuration register TBT_DMA_CFG_VS_CAP_17 for + * 20G and 40G retimer respectively. + * TBT_DMA_CFG_VS_CAP_17[0]: "speed indication valid" - 0->invalid, 1->valid + * TBT_DMA_CFG_VS_CAP_17[1]: "speed indication value" - 0->20 Gbps, 1->40 Gbps + */ + #define TBT_DMA_CFG_VS_CAP_17 0xe8 + + reg32 = pci_read_config32(dev, TBT_DMA_CFG_VS_CAP_17); + /* Skip programming if it had previously been configured */ + if (reg32 & 0x1) + return; + + if (usb4_gen) + reg32 |= 0x2; + else + reg32 &= 0x2; + + pci_write_config32(dev, TBT_DMA_CFG_VS_CAP_17, (reg32 | 0x1)); +} + void mainboard_silicon_init_params(FSP_S_CONFIG *params) { + struct device *dev; bool has_usb4; + bool usb4_gen2, usb4_gen3;
/* If device doesn't have USB4 hardware, disable tbt */ - has_usb4 = (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) || - fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3))); + usb4_gen2 = fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)); + usb4_gen3 = fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3)); + has_usb4 = (usb4_gen2 || usb4_gen3);
- if (!has_usb4) + if (!has_usb4) { memset(params->ITbtPcieRootPortEn, 0, ARRAY_SIZE(params->ITbtPcieRootPortEn) * sizeof(*params->ITbtPcieRootPortEn)); + return; + } + + dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0); + if (!dev) + return; + + /* usb4_gen2 for 20G and usb4_gen3 for 40G retimer */ + dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0); + mainboard_retimer_notify(dev, ((!usb4_gen2 && usb4_gen3) ? 1 : 0)); }
struct chip_operations mainboard_ops = {
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46571 )
Change subject: mb/google/volteer: Retrieve CBI about Retimer and notify TBT firmware ......................................................................
Patch Set 5:
(1 comment)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/46571/4/src/mainboard/google/voltee... File src/mainboard/google/volteer/mainboard.c:
https://review.coreboot.org/c/coreboot/+/46571/4/src/mainboard/google/voltee... PS4, Line 215: if (is_dev_enabled(dev)) {
braces {} are not necessary for single statement blocks
done
-
John Zhao (Code Review)