[S] Change in coreboot[master]: soc/amd/mendocino: Add FSP parameter for eDP power sequence adjustment

[Chris Wang (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held.

Chris Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74758 )

Change subject: soc/amd/mendocino: Add FSP parameter for eDP power sequence adjustment
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soc/amd/mendocino: Add FSP parameter for eDP power sequence adjustment

Add UPD parameter for eDP power sequence adjust.

The pwr_down_bloff_to_varybloff is set one unit per 4ms.

BUG=b:271704149
TEST=Build; Verify the UPD was pass to system integrated table.

Signed-off-by: Chris Wang 
Change-Id: Ibdf50db12d982b45edca205e8f4612deb702453d
---
M src/soc/amd/mendocino/chip.h
M src/soc/amd/mendocino/fsp_m_params.c
2 files changed, 21 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/74758/1

diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h
index 774ce5e..366bdd07 100644
--- a/src/soc/amd/mendocino/chip.h
+++ b/src/soc/amd/mendocino/chip.h
@@ -180,6 +180,9 @@
    /* Set for eDP power sequence adjustment timing from varybl to blon. The unit is set to
       one per 4ms*/
    uint8_t pwr_on_vary_bl_to_blon;
+	/* Set for eDP power sequence adjustment timing from bloff to varybloff. The unit is set to
+	   one per 4ms*/
+	uint8_t pwr_down_bloff_to_varybloff;

};

diff --git a/src/soc/amd/mendocino/fsp_m_params.c b/src/soc/amd/mendocino/fsp_m_params.c
index 453ce69..e3253c9 100644
--- a/src/soc/amd/mendocino/fsp_m_params.c
+++ b/src/soc/amd/mendocino/fsp_m_params.c
@@ -171,6 +171,7 @@

mcfg->dxio_tx_vboost_enable = config->dxio_tx_vboost_enable;
    mcfg->pwr_on_vary_bl_to_blon = config->pwr_on_vary_bl_to_blon;
+	mcfg->pwr_down_bloff_to_varybloff = config-> pwr_down_bloff_to_varybloff;

fsp_fill_pcie_ddi_descriptors(mcfg);
    fsp_assign_ioapic_upds(mcfg);