Change in coreboot[master]: soc/intel/tigerlake: Fix TCSS TBT PCIE root ports scope type

[John Zhao (Code Review)]

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40004 )

Change subject: soc/intel/tigerlake: Fix TCSS TBT PCIE root ports scope type
......................................................................

soc/intel/tigerlake: Fix TCSS TBT PCIE root ports scope type

TCSS TBT PCIE root ports scope type was mistakenly set to PCI_ENDPOINT.
Fix the scope type to be PCI_SUB.

BUG=b:141609884
TEST=Booted to kernel and verified no TBT PCIE root ports scope
type mismatch error in kernel log.

Change-Id: I844e7e9583992be496223fb51f24c5aa24fc7d21
Signed-off-by: John Zhao 
---
M src/soc/intel/tigerlake/acpi.c
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/40004/1

diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c
index 23fd970..7cd0102 100644
--- a/src/soc/intel/tigerlake/acpi.c
+++ b/src/soc/intel/tigerlake/acpi.c
@@ -1,6 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright (C) 2019-2020 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -246,7 +247,7 @@
    		unsigned long tmp = current;

current += acpi_create_dmar_drhd(current, 0, 0, tbtbar);
-			current += acpi_create_dmar_ds_pci(current, 0, 7, i);
+			current += acpi_create_dmar_ds_pci_br(current, 0, 7, i);

acpi_dmar_drhd_fixup(tmp, current);
    	}

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40004 )

Change subject: soc/intel/tigerlake: Fix TCSS TBT PCIE root ports scope type
......................................................................

Patch Set 1: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/40004/1/src/soc/intel/tigerlake/acp... 
File src/soc/intel/tigerlake/acpi.c:

https://review.coreboot.org/c/coreboot/+/40004/1/src/soc/intel/tigerlake/acp... 
PS1, Line 4:  * Copyright (C) 2019-2020 Intel Corp.
Please do not add copyright lines. We moved copyright notices to the AUTHORS file (and Intel is already there).

[John Zhao (Code Review)]

John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40004 )

Change subject: soc/intel/tigerlake: Fix TCSS TBT PCIE root ports scope type
......................................................................

Patch Set 1:

(1 comment)
> Patch Set 1: Code-Review+1
>
> (1 comment)

https://review.coreboot.org/c/coreboot/+/40004/1/src/soc/intel/tigerlake/acp... 
File src/soc/intel/tigerlake/acpi.c:

https://review.coreboot.org/c/coreboot/+/40004/1/src/soc/intel/tigerlake/acp... 
PS1, Line 4:  * Copyright (C) 2019-2020 Intel Corp.
> Please do not add copyright lines. […]

Ack

[John Zhao (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Shamile Khan, Paul Menzel, Angel Pons, Pratikkumar V Prajapati, Patrick Rudolph, Divya S Sasidharan,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40004

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: Fix TCSS TBT PCIE root ports scope type
......................................................................

soc/intel/tigerlake: Fix TCSS TBT PCIE root ports scope type

TCSS TBT PCIE root ports scope type was mistakenly set to PCI_ENDPOINT.
Fix the scope type to be PCI_SUB.

BUG=b:141609884
TEST=Booted to kernel and verified no TBT PCIE root ports scope
type mismatch error in kernel log.

Change-Id: I844e7e9583992be496223fb51f24c5aa24fc7d21
Signed-off-by: John Zhao 
---
M src/soc/intel/tigerlake/acpi.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/40004/2

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40004 )

Change subject: soc/intel/tigerlake: Fix TCSS TBT PCIE root ports scope type
......................................................................

Patch Set 2: Code-Review+2

Thanks!

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40004 )

Change subject: soc/intel/tigerlake: Fix TCSS TBT PCIE root ports scope type
......................................................................

Patch Set 2: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40004 )

Change subject: soc/intel/tigerlake: Fix TCSS TBT PCIE root ports scope type
......................................................................

soc/intel/tigerlake: Fix TCSS TBT PCIE root ports scope type

TCSS TBT PCIE root ports scope type was mistakenly set to PCI_ENDPOINT.
Fix the scope type to be PCI_SUB.

BUG=b:141609884
TEST=Booted to kernel and verified no TBT PCIE root ports scope
type mismatch error in kernel log.

Change-Id: I844e7e9583992be496223fb51f24c5aa24fc7d21
Signed-off-by: John Zhao 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40004
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/tigerlake/acpi.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c
index 9e7ff56..36c488b 100644
--- a/src/soc/intel/tigerlake/acpi.c
+++ b/src/soc/intel/tigerlake/acpi.c
@@ -235,7 +235,7 @@
    		unsigned long tmp = current;

current += acpi_create_dmar_drhd(current, 0, 0, tbtbar);
-			current += acpi_create_dmar_ds_pci(current, 0, 7, i);
+			current += acpi_create_dmar_ds_pci_br(current, 0, 7, i);

acpi_dmar_drhd_fixup(tmp, current);
    	}