Change in coreboot[master]: soc/qualcomm/common: clock: Cleanup common clock driver

[Ravi kumar (Code Review)]

Attention is currently required from: Taniya Das.
Hello Taniya Das,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/57447

to review the following change.

Change subject: soc/qualcomm/common: clock: Cleanup common clock driver
......................................................................

soc/qualcomm/common: clock: Cleanup common clock driver

The common clock driver exposes PLL configuration functions and also
different Agera PLL enable functions for the CPU PLLs.

BUG=b:182963902
TEST=Validated on qualcomm sc7180 and sc7280 development board.

Signed-off-by: Taniya Das 
Change-Id: Ifabe0508a37a841779965f4e38172f680e18d38a
---
M src/soc/qualcomm/common/clock.c
M src/soc/qualcomm/common/include/soc/clock_common.h
M src/soc/qualcomm/sc7180/clock.c
3 files changed, 3 insertions(+), 28 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/57447/1

diff --git a/src/soc/qualcomm/common/clock.c b/src/soc/qualcomm/common/clock.c
index 09cd95c..e83f979 100644
--- a/src/soc/qualcomm/common/clock.c
+++ b/src/soc/qualcomm/common/clock.c
@@ -236,29 +236,6 @@
    return CB_SUCCESS;
 }

-enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg)
-{
-	setbits32(cfg->reg_mode, BIT(PLL_BYPASSNL_SHFT));
-
-	/*
-	* H/W requires a 1us delay between disabling the bypass and
-	* de-asserting the reset.
-	*/
-	udelay(1);
-	setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT));
-	setbits32(cfg->reg_opmode, PLL_RUN_MODE);
-
-	if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) {
-		printk(BIOS_ERR, "ERROR: CPU PLL did not lock!\n");
-		return CB_ERR;
-	}
-
-	setbits32(cfg->reg_user_ctl, PLL_USERCTL_BMSK);
-	setbits32(cfg->reg_mode, BIT(PLL_OUTCTRL_SHFT));
-
-	return CB_SUCCESS;
-}
-
 /* Bring subsystem out of RESET */
 void clock_reset_subsystem(u32 *misc, u32 shft)
 {
diff --git a/src/soc/qualcomm/common/include/soc/clock_common.h b/src/soc/qualcomm/common/include/soc/clock_common.h
index 0911827..b924194 100644
--- a/src/soc/qualcomm/common/include/soc/clock_common.h
+++ b/src/soc/qualcomm/common/include/soc/clock_common.h
@@ -155,8 +155,6 @@
    				bool enable, int br_enable);
 enum cb_err agera_pll_enable(struct alpha_pll_reg_val_config *cfg);

-enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg);
-
 struct aoss {
    u8 _res0[0x50020];
    u32 aoss_cc_reset_status;
diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c
index aa289c4..4497b9c 100644
--- a/src/soc/qualcomm/sc7180/clock.c
+++ b/src/soc/qualcomm/sc7180/clock.c
@@ -164,12 +164,12 @@
    pll_cfg.l_val = l_val;

ret = clock_configure_enable_gpll(&pll_cfg, false, 0);
-	if (ret < 0)
+	if (ret != CB_SUCCESS)
    	return CB_ERR;

pll_cfg.reg_mode = &apss->pll.mode;
    ret = agera_pll_enable(&pll_cfg);
-	if (ret < 0)
+	if (ret != CB_SUCCESS)
    	return CB_ERR;

gfmux_val = read32(&apss->cfg_gfmux) & ~GFMUX_SRC_SEL_BMSK;
@@ -224,7 +224,7 @@
    if (clk_type >= MDSS_CLK_COUNT)
    	return CB_ERR;

-	/* Enable clock*/
+	/* Enable clock */
    return clock_enable(mdss_cbcr[clk_type]);
 }