Change in coreboot[master]: [WIP]nb/intel/x4x/raminit: Make programming crossclock suppo...

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19871 )

Change subject: [WIP]nb/intel/x4x/raminit: Make programming crossclock support DDR3
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[WIP]nb/intel/x4x/raminit: Make programming crossclock support DDR3

A few values need to be verified.

Change-Id: I86b70e06c81817854994b7feddf9f3638fd16198
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/x4x/raminit_ddr23.c
1 file changed, 15 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/19871/1

diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index 9cb29ef..253b5ee 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -71,6 +71,7 @@
 static void program_crossclock(struct sysinfo *s)
 {
    u8 i, j;
+	u32 reg32;
    MCHBAR16(0xc1c) = MCHBAR16(0xc1c) | (1 << 15);

static const u32 clkxtab[6][3][13] = {
@@ -83,7 +84,7 @@
    	{{0x1f1f1f1f, 0x1a07070b, 0x00000000, 0x10000000,
    	  0x20010208, 0x04080000, 0x10010002, 0x00000000,
    	  0x00000000, 0x02000000, 0x04000100, 0x08000000,
-		  0x10200204},
+		  0x10200204}, /* Check item[1] : 0x0d07070B ? */
    	/* FSB 1067 */
    	{0x6d5b1f1f, 0x0f0f0f0f, 0x00000000, 0x20000000,
    	 0x80020410, 0x02040008, 0x10000100, 0x00000000,
@@ -104,7 +105,7 @@
    	{0x07070707, 0x06030303, 0x00000000, 0x00000000,
    	 0x08010200, 0x00000000, 0x04000102, 0x00000000,
    	 0x00000000, 0x00000000, 0x00020001, 0x00000000,
-		 0x02040801},
+		 0x02040801}, /* item[9] = 0x00020100 ?*/ /* item[11] = 0x04080100 */
    	/* FSB 1333 */
    	{0x0d0b0707, 0x3e1f1f2f, 0x01010000, 0x00000000,
    	 0x10020400, 0x02000000, 0x00040100, 0x00000000,
@@ -135,7 +136,13 @@
    j = (u8)s->selected_timings.fsb_clk;

MCHBAR32(0xc04) = clkxtab[i][j][0];
-	MCHBAR32(0xc50) = clkxtab[i][j][1];
+	reg32 = clkxtab[i][j][1];
+	if (s->spd_type == DDR3 && s->max_fsb == FSB_CLOCK_1333MHz
+		&& s->selected_timings.mem_clk == MEM_CLOCK_800MHz) {
+		reg32 &= ~(0xFF000000);
+		reg32 |= 0x3d << 24;
+	}
+	MCHBAR32(0xc50) = reg32;
    MCHBAR32(0xc54) = clkxtab[i][j][2];
    MCHBAR8(0xc08) = MCHBAR8(0xc08) | (1 << 7);
    MCHBAR32(0x6d8) = clkxtab[i][j][3];
@@ -1797,8 +1804,11 @@
    	// Clear host clk gate reg
    	MCHBAR32(0x1c) = MCHBAR32(0x1c) | 0xffffffff;

-		// Select DDR2
-		MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4;
+		// Select type
+		if (s->spd_type == DDR2)
+			MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4;
+		else
+			MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0x4;

// Set freq
    	MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0x70) |