Change in coreboot[master]: mb/google/mancomb: Update GPIO configuration

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52177 )

Change subject: mb/google/mancomb: Update GPIO configuration
......................................................................

mb/google/mancomb: Update GPIO configuration

BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai 
Change-Id: Ie3917c10ecf37c914dbadce5949b8f4f772abd5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52177
Tested-by: build bot (Jenkins) 
Reviewed-by: Mathew King 
---
M src/mainboard/google/mancomb/variants/baseboard/gpio.c
1 file changed, 11 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Mathew King: Looks good to me, approved

diff --git a/src/mainboard/google/mancomb/variants/baseboard/gpio.c b/src/mainboard/google/mancomb/variants/baseboard/gpio.c
index cd86f9c..1e39853 100644
--- a/src/mainboard/google/mancomb/variants/baseboard/gpio.c
+++ b/src/mainboard/google/mancomb/variants/baseboard/gpio.c
@@ -53,8 +53,8 @@
    /* HUB_RST_L */
    PAD_GPO(GPIO_24, LOW),
    /* GPIO_25: Not available */
-	/* PCIE_RST0_L */
-	PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
+	/* TODO: change back to PCIE_RST_L when we figure out why PCIE_RST doesn't go high. */
+	PAD_GPO(GPIO_26, HIGH),
    /* PCIE_RST1_L */
    PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
    /* GPIO_28: Not available */
@@ -93,7 +93,7 @@
    PAD_GPI(GPIO_84, PULL_NONE),
    /* AGPIO85 */
    PAD_NC(GPIO_85),
-	/* SPI_CLK2 */
+	/* ESPI_SOC_CLK */
    PAD_NF(GPIO_86, SPI_CLK, PULL_NONE),
    /* AGPIO87 */
    PAD_NC(GPIO_87),
@@ -116,6 +116,8 @@
    PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE),
    /* ESPI1_DATA3 */
    PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE),
+	/* ESPI_ALERT_L */
+	PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE),
    /* EGPIO109 */
    PAD_NC(GPIO_109),
    /* GPIO_110 - GPIO_112: Not available */
@@ -169,6 +171,12 @@
    PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
    /* I2C3_SDA */
    PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
+	/* PCIE_RST0_L */
+	PAD_GPO(GPIO_26, HIGH),
+	/* ESPI_CS_L */
+	PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
+	/* ESPI_SOC_CLK */
+	PAD_NF(GPIO_86, SPI_CLK, PULL_NONE),
    /* ESPI1_DATA0 */
    PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE),
    /* ESPI1_DATA1 */