New patch to review for coreboot: soc/intel/common: Add reset.c to postcar

[Furquan Shaikh]

Furquan Shaikh ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17182

-gerrit

commit a49a1ef3f62967d3849933c57b2d3f79159359ce
Author: Furquan Shaikh 
Date:   Fri Oct 28 14:55:46 2016 -0700

soc/intel/common: Add reset.c to postcar

ramstage_cache_invalid which was added in
    I83fe76957c061f20e9afb308e55923806fda4f93 (review.coreboot.org/#/c/17112)
    requires hard_reset to be defined in postcar stage.

BUG=None
    BRANCH=None
    TEST=Compiles successfully for reef.

Change-Id: I283277c373259e0e2dfe72e3c889ceea012544f2
    Signed-off-by: Furquan Shaikh 
---
 src/soc/intel/common/Makefile.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index 888c657..38903a0 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -15,6 +15,7 @@ romstage-y += util.c
 romstage-$(CONFIG_MMA) += mma.c

postcar-y += util.c
+postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c

ramstage-y += hda_verb.c
 ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c