Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 )
Change subject: soc/intel/skylake: Configure ASPM and L1 substates for PCH root ports
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Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39538/6/src/soc/intel/skylake/chip....
File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/39538/6/src/soc/intel/skylake/chip....
PS6, Line 221: PcieRpAspm
This disabled ASPM on both my root ports. […]
Yes, you probably want something like the L1 substate thing
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Gerrit-Project: coreboot
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