Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...

[Nico Huber (Code Review)]

Attention is currently required from:  Felix Singer, Tim Crawford, Jeremy Soller.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 )

Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit
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Patch Set 5:

(4 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/49104/comment/c77056a5_a3894706 
PS5, Line 14: the TigerLake FSP Integration Guide.
I couldn't find it, can you be more specific?

(I did find example code, but nothing about the behavior when using
a dummy, all-zero entry.)

https://review.coreboot.org/c/coreboot/+/49104/comment/6f419d62_0f7660e2 
PS5, Line 23: Tested by checking lspci output on System76 galp3-c, oryp5, oryp6.
I can't find any of them in the tree. Which FSP do they use?

File src/soc/intel/cannonlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/49104/comment/67e7ddb7_ae0581c1 
PS5, Line 552: 0
This looks like a valid address to me: offset 0 of PCI 0:00.0, or did I
miss something? If that's the case, FSP would try to write the VID/DID
pair of that device which seems like a crude hack. Shouldn't we use an
address of a known, non-existent device?

https://review.coreboot.org/c/coreboot/+/49104/comment/32ace12a_142ae28f 
PS5, Line 561: 	dev = pcidev_path_on_root(PCH_DEVFN_XHCI);
             : 	if (dev)
             : 		pci_dev_set_subsystem(dev, dev->subsystem_vendor,
             : 			dev->subsystem_device);
             : 
             : 	dev = pcidev_path_on_root(PCH_DEVFN_HDA);
             : 	if (dev)
             : 		pci_dev_set_subsystem(dev, dev->subsystem_vendor,
             : 			dev->subsystem_device);
Alternatively to a dummy entry, why not move this into the table?