Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47687 )
Change subject: mb/google/puff/var/dooly: update USB2 type-c strength ......................................................................
mb/google/puff/var/dooly: update USB2 type-c strength
Based on USB DB report.
BRANCH=puff BUG=b:163561808 TEST=build and measure by EE team.
Change-Id: I379987b6d6d2a7aef33d4c42e589dc52d40205a3 Signed-off-by: Tony Huang tony-huang@quanta.corp-partner.google.com --- M src/mainboard/google/hatch/variants/dooly/overridetree.cb 1 file changed, 16 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/47687/1
diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index 6e23448..efa7d71 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -27,7 +27,14 @@ .pre_emp_bias = USB2_BIAS_11P25MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A Port 0 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 0 + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port 0 register "usb2_ports[2]" = "{ .enable = 1, .ocpin = OC3, @@ -37,7 +44,14 @@ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A Port 1 register "usb2_ports[3]" = "USB2_PORT_EMPTY" - register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 1 + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port 1 register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # USB cam register "usb2_ports[6]" = "USB2_PORT_EMPTY" register "usb2_ports[7]" = "USB2_PORT_EMPTY"
Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47687 )
Change subject: mb/google/puff/var/dooly: update USB2 type-c strength ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47687 )
Change subject: mb/google/puff/var/dooly: update USB2 type-c strength ......................................................................
mb/google/puff/var/dooly: update USB2 type-c strength
Based on USB DB report.
BRANCH=puff BUG=b:163561808 TEST=build and measure by EE team.
Change-Id: I379987b6d6d2a7aef33d4c42e589dc52d40205a3 Signed-off-by: Tony Huang tony-huang@quanta.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47687 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Sam McNally sammc@google.com --- M src/mainboard/google/hatch/variants/dooly/overridetree.cb 1 file changed, 16 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Sam McNally: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index 6e23448..efa7d71 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -27,7 +27,14 @@ .pre_emp_bias = USB2_BIAS_11P25MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A Port 0 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 0 + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port 0 register "usb2_ports[2]" = "{ .enable = 1, .ocpin = OC3, @@ -37,7 +44,14 @@ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A Port 1 register "usb2_ports[3]" = "USB2_PORT_EMPTY" - register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 1 + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port 1 register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # USB cam register "usb2_ports[6]" = "USB2_PORT_EMPTY" register "usb2_ports[7]" = "USB2_PORT_EMPTY"
-
Patrick Georgi (Code Review) -
Sam McNally (Code Review)
-
Tony Huang (Code Review)