[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC

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Attention is currently required from: Elyes Haouas, Felix Singer, Frans Hendriks, Jérémy Compostella, Paul Menzel, Shuo Liu, Vasiliy Khoruzhick.

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Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
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Patch Set 49:

(1 comment)

File src/soc/intel/snowridge/chip.c:

https://review.coreboot.org/c/coreboot/+/83321/comment/005295ce_7f386ce4?usp... :
PS15, Line 418: 	}
> Will the common pci dev enabler be called as well?

Seems there is no `enable` method in the default PCI or PCIe device operations, and the `PCI_COMMAND_SERR` is also not set by common code. Thus, this function will set the SERR bit of all PCH static devices if they are marked as enabled and disable responding to IO and memory requests if they are marked as disabled.